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Mini-Internet for multicore processors proposed

25 Apr 2012

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Li-Shiuan Peh, an associate professor of electrical engineering and computer science at the Massachusetts Institute of Technology (MIT), has suggested that cores should communicate the same way computers hooked to the Internet do: by bundling the information they transmit into "packets." Each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network as a whole.

Peh and her colleagues have established theoretical limits on the efficiency of packet-switched on-chip communication networks, but they also present measurements performed on a test chip in which they came very close to reaching several of those limits.

In principle, multicore chips are faster than single-core chips because they can split up computational tasks and run them on several cores at once. Cores working on the same task will occasionally need to share data, but until recently, the core count on commercial chips has been low enough that a single bus has been able to handle the extra communication load. The 10-core chips found in high-end servers frequently add a second bus, but that approach won't work for chips with hundreds of cores.

For one thing, Peh says, "buses take up a lot of power, because they are trying to drive long wires to eight or 10 cores at the same time." In the type of network Peh is proposing, each core communicates only with the four cores nearest it.

In an on-chip network, however, a packet of data traveling from one core to another has to stop at every router in between. Moreover, if two packets arrive at a router at the same time, one of them has to be stored in memory while the router handles the other. Many engineers, Peh says, worry that these added requirements will introduce enough delays and computational complexity to offset the advantages of packet switching.

Peh and her colleagues have developed two techniques to address these concerns. One is "virtual bypassing." In the Internet, when a packet arrives at a router, the router inspects how it addresses information before deciding which path to send it down. With virtual bypassing, however, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. In her group's test chips, Peh says, virtual bypassing allowed a very close approach to the maximum data-transmission rates predicted by theoretical analysis. The other technique is something called "low-swing signaling." Digital data consists of ones and zeroes, which are transmitted over communications channels as high and low voltages. With its combination of virtual bypassing and low-swing signaling, the researchers' test chip consumed 38 percent less energy than previous packet-switched test chips.




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