Layout optimization techniques to identify spare buffer logic for post-mask engineering change order15 Jun 2012
Implementing Engineering Change Orders (ECO) is a very common step during the design phase of a System-on-Chip (SoC). There can be diverse reasons for incorporating an ECO within the design.
1. Planned ECO: Sometimes the need for an ECO can be pre-conceived by the designer. For instance, there can be situations when an IP needs to be used later in the ASIC design cycle and hence the designer plans the activities appropriately so that the design phase is not gated. But having said that, mostly the occurrence of an ECO is fairly random within the design cycle.
2. Functional Modification: An ECO can also result from functional modifications of the design specifications which may be necessary if the customer calls for some additional features, or if the application software demands the feature to be deployed in hardware.
3. Design Issues: There can be design issues which can be caught either in Gate-Level Simulations (GLS) or silicon results of some prior testchip in a similar technology.
To implement the ECO in logic gates, the designer needs an optimum solution as addition of extra gates will result in re-fabrication of base-layer masks like active, polysilicon, nitride and implant layers which are costlier than the interconnect masks. So ideally a designer would want to incorporate the logic from the existing logic only to negate the cost impact arising due to re-fabrication.
Shortcoming with existing modus operandi across industry
Incorporating the ECO using extra logic gates may affect the overall timing and routability of the design specifically, when the ECO logic is fairly large, and the affected module placement density tends to 100 percent.
Existing methodologies of meeting this problem involve addition of extra spare gates within each module during physical synthesis of the design, so that if an ECO occurs, the existing spare gates could be used later to incorporate modification in the design. This would negate the need of adding of extra logic. However, there are certain limitations of this methodology.
Limitations of existing methodology
1. The designer cannot predict the optimal number of spare gates within a module to absorb any ECO. For e.g., let's assume that the Functional ECO needs 10 buffers to be connected in a chain. But the available spare cell modules have only six buffers, which forces the design team to do a respin of the SoC because of non-availability of buffers/inverter (pair). Essentially, the limitation is that the designer invariably places either extra redundant logic within one module or limited spare gates within another module.
2. A fairly large ECO would invariably result in hold timing violations and design rule violations (DRV) like max-transition or max-drive strength of a logic gate. This would trigger the need of additional redundant buffers for fixing hold violations or to improve the slew-rate of signals prone to DRVs.
The article presents a solution where existing layout can be used to overcome the need of buffers/inverter (pair). Please keep in that that while the addition of redundant NAND/NOR gates and extra flip-flops/latches may be necessary within a spare module but addition of redundant buffers and inverters is not necessary.
Essentially, the article tries to demonstrate a novel methodology of recovering buffer/inverter logic from the existing layout using optimization techniques.
Figure 1: Basic Algorithm which needs to be implemented for a window of size (x1,y1,x2,y2).
Click to enlarge
Pseudocode for generating window size:
while x < x2
while y < y2
x' = x + a, y' = y + b;
if x > x2 or y > y2
The coordinates of each window generated are given by (x, y, x', y'). Here, a, b needs to be design- and technology-dependent. If the sea of gates (SoG) area of the SoC is of the order of 7mm² or more, one needs to look into the computational complexity for calculating the window size.
DESCRIPTION OF LAYOUT BASED ECO
As shown in the above flowchart, the idea revolves around identifying the non-critical buffers (with respect to timing slack). It happens invariable that while implementing an ECO, a buffer from the spare cell module is used. Now, the placement of this buffer is randomized and using it results in a DRV rule violations.
For e.g. let's assume a BUFX8 is used to drive five fanouts. Total capacitive load (both wire and pin) comes out to be 200fF. Now according to the spice characteristics of this buffer, any load above 150fF gives a bad output slew. This bad output slew not only results in a max_transition violation but also affects the timing of the fanout cone.
Hence, in such a case it would be wise to follow the above algorithm:
1. Identify the target points of ECO: Identify the location of the start and end points where the buffer element is desired to be placed. This location shall drive the size of the window which can be searched for the non-critical buffer/inverter(pair)
2. Decide the size of the window: This is solely on the discretion of the designer. He can choose the window size according to the technology. If the maximum load that a Buffer can drive is 200fF, then the window size should be changed accordingly
3. Identification of buffers/inverter (pair): Now the algorithm would run on the specified window and try to identify all the buffer/inverter(pair) present in the marked location
4. Calculating timing slack: Once the buffer/inverter (pair) is marked, algorithm shall try to find out the timing slack through these cells. If these are timing critical, then such buffer/inverter (pair) is unmarked. ONLY THAT BUFFER/INVERTER (PAIR) SHALL BE KEPT MARKED REMOVING WHICH DOES NOT AFFECT THE EXISTING TIMING PROFILE OF THE DESIGN.
5. Final Step: Now the marked buffer/inverter (pair) can be used for ECO.
Layout optimization and making use of redundant cells can aid a designer to achieve the goal of assimilating a complex ECO, later in the design phase of a multimillion gate SOC, without impacting the overall time-to-market of the product.
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