The following article proposes a new technique which leads to virtually infinite reservoir of spare cells hence making possible to implement complex and big engineering change orders (ECOs) without base layer change thus generating huge revenues for chip design companies. The algorithm involves restructuring of current logic to generate new spares gates required for ECO thus guarantees that ECO is implemented by desired number of spare cells. The paper proposes use of universal nand/nor gates as hold buffers which can be recovered as spare cells in form of redundant hold buffers. This technique results in lesser leakage design power in comparison to conventional chips without any area overhead. The proposed approach is generic approach across all type of designs and for all technology nodes.

INTRODUCTION
The post silicon ECOs are important part of design cycle. The post silicon validation bug detection and addition of new features necessitates a revision of around 60 percent of chips. Implementing ECOs in metal only is a challenge that averts base layer change. In modern technologies, the transistor masks account for about 68 percent of the total mask costs. So aim is to implement ECOs with only metal layer changes. Numerous techniques to cater timing and routing issues do exist. Averting base layer change especially when required ECO cells are more than available spare cells poses major challenge.

In this article, we are proposing a novel algorithm which generates desired type of spare cells by restructuring surrounding non timing critical logic. Here we are not merely dependent upon availability of spare cells. Proposed algorithm caters equally to timing, routing and averting base layer change in case when required ECO logic exceeds spare cells present in SOC. Our algorithm explores:

1) Possibility of restructuring digital logic;

2) Reusing freed cells which are spared as a result of some ECO to generate new spare cells;

3) Using pair of NAND and NOR as paired inverter to fix hold timing in design and using/swapping these cells to implement ECO logic at the time of ECO.

BASIC ECO TECHNIQUES
The most of the work done on ECO implementation deals with mapping ECO constraints equations to available spare cells and then implement it with minimum routing layers. Various available techniques include the cone resynthesis ECO methodology to cause minimum perturbation to the gate level netlist, the iterative method to generate feasible mapping solutions for an ECO problem with spare cells, optimally map the logic onto already placed recycled and spare cells such that summation of wire lengths for the placed and routed netlist is minimized.

ECO LOGIC GENERATION
Post silicon ECO implementation in its nascent stage and involves numerous intricacies. Spare cell approach is presently employed to cater its need. If spare cells are unable to suffice for required ECO logic, change is rendered non-ecoable with metal only layers. Such unmanageable ECOs necessitate base layer change and more cost is incurred. This paper proposes a methodology that could potentially avert base layer changes.

In any SOC design cycle, there may be redundant buffers due to various factors:

� Fixing hold/DRV at various stages in the design requires lot of buffers due to very stringent constraints.

� Skew scenario changes from Post CTS to Post Route stage.

� Multimode-Multicorner optimization for Hold.

� Improvement in certain HOLD critical paths due to noise uncertainty.

� Pessimistically fixing DRVs.

Such redundant buffers cannot be used at the time of ECO to implement ECO logic. Here, we incept our algorithm to replace paired buffers with a pair of basic Nand/Nor gates. These NAND/NOR gates can be used to implement the ECO logic as they are the basic digital components. The used gate, if resulting timing violation, can in turn be realized using any gate as a buffer element or using wire delays.

TABLE 1.

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Various factors govern the selection of hold buffers like Area, Internal power, Leakage power and Cell delay. A comparison matrix between nand cell and buffer is shown in Table 1 (for cmos90 process).

It can be seen that leakage and internal power is less for NAND gate compared to buffer due to two reasons. Firstly, buffer is two stage device compared to single stage of NAND/NOR gates and secondly NAND gate posses stack of three transistors compared to two for buffer. Same factors contribute to the fact that NAND gate posses 16 percent higher delay compared to that buffer. This ensures lesser number of hold buffers required during Hold optimization. Therefore its apt to deduce that NAND gate is better candidate for hold fixing over buffer. Underlying concept lies in replacing pair of buffers with pair of NAND or NOR gates so that functionality of design remains intact. Thus ECO capability of a SOC depends upon availability of NAND/NOR gates for implementation.

NAND and NOR gates are considered universal gates and any complex logic could be functionally implemented by aptly using universal gates. The major limitation of such implementation is timing criticality. A simple logic like A!B could be implemented via three NAND gates. To deal with such limitation, functional logic optimization is proposed. Figure 1 shows slack distribution versus number of endpoints.

Figure 1.

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The graph depicts that major chunk of design is relaxed from static timing analysis front. Suppose ECO required is addition of complex cell with function A!B+!C!D. Such complex logic requires 8 NAND elements. If required ECO is becoming timing critical with NAND/NOR only gates, then we implement the logic using the complex gate present in the relaxed portion of the timing graph, lying in the vicinity of ECO and implement the used gate using NAND gates.

Thus above mentioned functional re-structuring technique is used to overcome limitation posed by timing critical ECOs.

PROCEDURE AND ALGORITHM
This section deals with the proposed algorithm. Here, NAND/NOR gates are required during hold optimization. In case of post-silicon ECO, if required ECO could not be implemented using spare/freed cells, required number of NAND/NOR cells are freed based on availability of timing slack. In case ECO logic realized using NAND/NOR gates is timing critical, functional restructuring is performed where complex functional logic of non-timing critical logic is replaced by NAND/NOR implementation as explained in Flowchart 1.

Flowchart 1.

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PHYSICAL DESIGN ISSUES
Factors like routing congestion and placement needs to be considered along with timing and restructuring. Below mentioned flowchart caters to such requirements in optimized way. Non-critical complex logic is searched in vicinity of ECO region via increasing angular constraints by 100 microns until nearest non critical timing logic is replaced by spare cells.

Flowchart 2.

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CONCLUSION
A methodology that is potent enough to avert base layer change is proposed. Here, ECO spare cell database is numerously increased to implement complex ECO possible. This article also deals with routing, timing and restructuring approach in a novel way. Saving of enormous cost incurred necessitates extensive usage of proposed concept for future SOC designs

Freescale Semiconductor