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Cadence updates simulator with improved low-power verification

10 May 2013

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A new version of the Incisive Enterprise Simulator has been released by Cadence Design Systems.. The 13.1 release of Cadence Incisive Enterprise Simulator addresses low-power verification challenges for advanced modelling, debug, and power format support and to provide faster verification for today's most complex SoCs. The updated software boasts features that improve low-power verification productivity of complex SoCs by 30 per cent.

"We successfully ran the Unified Power Format (IEEE 1801 / UPF) simulation with the Incisive Enterprise Simulator to identify power domains, verify isolation, and more," said STMicroelectronics' R&D design manager David Vincenzoni. "The tool works well and we applaud Cadence for adding the new advanced verification capabilities and IEEE 1801 support that will help speed the completion of our low-power SoCs."

The new debug features in Incisive SimVision Debugger provide simple visualisation and interactive debug of both complex text-based power intent standards. Other simulator enhancements include additional SystemVerilog support and faster elaboration to turn around simulation jobs much more quickly. Enhanced support for CPF and newly added support of IEEE 1801 will make these enhancements available to all low-power engineers.




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