Tempus solution by Cadence boasts quicker closure23 May 2013 | Stephen Evanczuk
Share this page with your friends
According to Cadence, engineers currently contend with a growing number of timing views and increased processing requirements for analysis. As a result, time spent in timing closure for 20nm designs accounts for up to 40 per cent of the design flow.
Figure 1: Timing closure accounts for an increasing share of project schedules with the increase in number of timing views with advanced processes (left) and associated increase in runtime for associated with a growing number of views (right). Source: Cadence Design Systems.
With Tempus, Cadence is tackling the timing closure bottleneck by addressing what it considers the three key issues facing timing closure: Performance, Accuracy and Closure.
Tempus supports massively parallel computation based on relatively low-cost processing nodes managed by industry standard workload platforms such as LSF (Load Sharing Facility). The solution also combines advanced foundry-validated process models with a new path-based analysis approach to provide more accurate timing analysis that delivers timing results that are 3 per cent less pessimistic timing, a margin that can be used to complete signoff sooner or to improve power performance.
The solution also brings a physical view of the design into timing analysis, allowing engineers to identify and fix problems in the same environment and be assured the fix is correct across all views. This capability enables a "physically-aware" ECO capability that can result in up to a 10x productivity improvement in design closure.
Figure 2: . Cadence Tempus melds physical design views with a multi-mode, multi-corner capability and physically-aware optimisation to support a physically-aware ECO flow capable of significantly speeding timing closure. Source: Cadence Design Systems.
Cadence is targeting Q3 2013 for general availability of the Tempus Timing Signoff Solution.
- Stephen Evanczuk
Want to more of this to be delivered to you for FREE?
Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.
Got to make sure you're not a robot. Please enter the code displayed on the right.Please enter the valid code. Sorry, you have reached the maximum number of requests allowed. You may wish to try again after a few hours.
Time to activate your subscription - it's easy!
We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.
We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.
In this platform, TSMC offers multiple processes to provide significant power reduction benefits for IoT and wearable products and a comprehensive design ecosystem to accelerate time-to-market.