Cadence data converter IP line suited for WiGig14 Oct 2013
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Cadence Design Systems has rolled out a product line of silicon-proven data converter IP for advanced 28nm node for wired and wireless communications applications. The portfolio includes 7bit 3GSPS dual ADC and DAC, 11bit 1.5GSPS dual ADC, and 12bit 2GSPS dual DAC. The products are suited for designers working with emerging high-speed protocols such as WiGig (802.11ad), which functions on a 60GHz spectrum with potential data throughput up to 7Gbit/s, as well as LTE and LTE Advanced.
The data converter IP cores can be combined to form a complete analogue front end (AFE) IP solution. The Cadence family of IP addresses have potential applications in wired and wireless communications, infrastructure, imaging and software-defined radios.
"The ability to easily integrate the Cadence Data Converter IP in advanced process nodes eliminates the need to go 'off-chip' and allows designers to take full advantage of the system benefits of integrating both the digital and analogue content into a single complex SoC," said Martin Lund, senior vice president of the Cadence IP Group. "This translates to longer battery life, smaller thermal profile, and lower overall system cost."
"The Cadence analogue high speed family of IP will empower and enhance the potential growth of WiGig (802.11ad) usage in mobile devices, opening the door to the evolution of emerging markets and 'Internet of Things' ecosystem," said Richard Wawrzyniak, senior market analyst, Semico Research. "The throughput and speed of WiGig is largely dependent on the data sampling rate of the ADCs and DACs used in the interface. Increasing these sampling rates, which the Cadence analogue IP does, breaks the device dependencies on non-CMOS or older process nodes, and allows for much higher performance."
The ADC IP cores are developed with a parallel Successive Approximation Array (SAR) architecture, producing extremely fast and scalable sample rates. High Effective-Number-of-Bits (ENOB) values are achieved with an implementation and built-in background auto calibration, allowing for conversion and consistent performance. The Cadence IP includes features such as differential data inputs, reference and timing generator, internal offset correction, and voltage regulators for improved supply noise immunity.
The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for integration into an SoC. The DACs include digital gain control and required reference circuitry.
All the IP includes multi-level power-down modes for additional power savings, a built-in analogue test bus for design testability, and single-ended CMOS or differential Current-Mode Logic (CML) clock inputs for a flexible clock interface.
The Cadence IP provides matching dual channels for communication systems where these are desired, simplifying implementation and reducing risk, and a standard CMOS process target for easy manufacturing.
The Cadence 28nm Data Convertor IP family is now available. Cadence also offers a full portfolio of 28nm IP that includes interface, memory, SerDes, and other analogue IP beyond data converters.
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