Solido Design Automation said that it took the wraps off a new technology that promises to help designers of analog/mixed-signal, custom digital, and memory integrated circuits (ICs) ensure that their transistor-level designs will work across all manufacturing process variations.
Solido's cofounder and CEO, Amit Gupta, said, "Semiconductor companies are suffering because existing design automation technologies and tools lack fundamental capabilities needed for today's nanometer manufacturing processes. Solido's goal is to provide a path to success for these companies. Our technology will give semiconductor designers a way to stop over-designing their chips and get them into customers' hands faster than ever before."
Called transistor-level statistical design and verification, the new Solido patent-pending technology leverages statistical process information to make designs robust to process variations. It incorporates such methodologies as statistical sampling, tradeoff analysis, circuit characterization, and circuit enhancement to discover problems and help designers explore opportunities to compensate for those problems. In turn, designs are better able to withstand process variations and meet specifications without being over-designed.
Solido said that its technology addresses the global and local statistical variations that occur in semiconductor devices designed for manufacturing processes at or below 180 nanometers. Global statistical variations include lot-to-lot and die-to-die manufacturing variations; local statistical variations include device mismatch. Such variations can have a negative impact on manufacturing yield, and can cause circuits to fail altogether. The new technology from Solido will be integrated into existing industry-standard analog, mixed-signal, and custom design flows.
Solido Design Automation
