Minimizing power in 65nm FPGA devices

With FPGA devices offering above 500MHz performance, ASIC-like densities and more than 1000 I/O pins, the power consumed by FPGAs is becoming an important design factor for complex systems design. Systems designers now need to accommodate for power consumption in these big FPGAs especially in the nano-technology process domain where smallergeometries lead to higher power.

Altera has introduced innovative architectural and process technology approaches to minimizing power in FPGAs without compromising on density and performance.

POWER CONSUMPTION IN FPGAS

There are two major components to power: static and dynamic. Static power is the power consumed by the FPGA after it is programmed but with no clocks operating and no signals toggling (including I/O pins). Dynamic power is the additional power consumed through the dynamic operation of the device caused by signals toggling (including clocks and I/O being active) and capacitive loads charging anddischarging.

The static power in FPGAs is due to the leakage current. The sources of static leakage current in 65nm are shown in (Figure 1) and (Table 1). Table 1 shows that the dominant component of leakage current is sub-threshold leakage. The leakage current worsens at smaller process technologies such as 65nm (Figure 2).

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(Figure 3) shows that the main variables affecting dynamic power are capacitance charging, the square of the supply voltage, and clock frequency. While the power reduction declines for an equivalent circuit from process node to process node, the reality is that FPGA capacity keeps doubling and the maximum clock frequency keeps going up.

PROCESS TECHNOLOGY FOR POWER REDUCTION

Several process technology approaches exist that can minimize power or increase performance. (Table 2) shows the different techniques that are used with submicrontechnologies.

In addition to the process technology-based approaches to power reduction, Altera has also introduced several architectural innovations for reducing power consumption.

Programmable power technology

With Programmable Power Technology in Stratix III, Altera has introduced a radical method of reducing power in high-endFPGAs.

Traditionally, all highperformance FPGAs are implemented with a highperformance fabric where every logic element (LE) provides the maximum performance (and thereby higher leakage power). Altera's programmable power technology takes advantage of the fact that most circuits in a design have excess slack and therefore do not require the highest performance.

Programmable Power Technology enables Stratix III logic fabric to be programmed at the logic array block level to provide low power. Thus, a small percentage of logic that require high performance get a high-speed setting while the rest of the logic get a low-power setting (Figure 4).

This technology results in a 70% reduction in leakage power for the low-power logic sections. Unused logic resource such as DSP blocks in low-power mode further decreases power. Thus Programmable Power Technology enables an optimal combination of high-performance logic to achieve performance, and low-power logic to achieve lowest power possible.

This programmability between high-speed and low-power setting is controlled on a per-tile basis (each tile consists of two LABS, or a LAB and DSP block, or a TriMatrix memory, along with associated routing in each case). For example: with the largest Stratix III FPGA, over 5000 tiles can be individually controlled for high speed or low power (Figure 5).

Altera's Quartus II design software automatically selects the high-performance mode or lowpower mode for each tile based on the design without any manual effort for the designer.

The Quartus II software tool automatically optimizes the design to meet the timing constraints while minimizing power using the PowerPlay Analyzer (Figure 6).

Selectable core voltage

In addition to programmable power technology, Stratix III selectable core voltage allows the designer to use a 0.9 or 1.1V core voltage based on performance requirements. The 0.9V core voltage provides the overall minimum dynamic and leakage power, while the 1.1V core voltage delivers the overall highestperformance.

The selectable core voltage is implemented during board design by setting the selectable core voltage input as 0.9 or 1.1V.

In combination, the programmable power technology and selectable core voltage deliver various performance and power operating points that achieve over 50% power reduction at 1.1V compared to previous generation of FPGAs.

CONCLUSION

The breakthroughs to the Stratix III architecture, programmable power technology and selectable core voltage, enable the lowest possible power for high-end FPGAs. In addition, Stratix III FPGAs continue Altera's practice of using industry-best practices in process and circuit design to reduce power by 50% over previous generation devices. The Quartus II design software has been developed for the best power analysis and optimization in the entire FPGA industry. Overall, the Stratix III solution provides the performance designers need at the lowest possible power of any high-end FPGA.