A logical approach to NVM integration in SoC design
( 01 Apr 2007 )
by Ann De Vries and Yanjun MA, Impinj
SoC designers have several options for integrating NVM (nonvolatile memory) into their designs, so it's wise to weigh the availability and numerous trade-offs before jumping headfirst into integrating NVM into your SoC.
Increasingly, ICs require embedded NVM (nonvolatile memory). The popularity of consumer appliances such as MP3 players - with their asSoCiated need for digital-rights management - and security considerations, for example, drive this trend. At the same time, recent technological advancements provide designers with many options for integrating on-chip NVM. Understanding the trade-offs among the various technologies equips designers with the knowledge necessary to create the best design in the most cost-effective manner.
Generally, when SoC (system-on-chip) designs require a small amount of NVM, designers might select mask-programmable ROM, battery-backed SRAM, or OTP (one-time-programmable) fuses. For certain design trades, EEPROM and Flash memory make sense. Now, logic-CMOS NVM, also known as logic NVM, is also an option. What are the advantages or disadvantages of each choice? How does a choice affect system performance, chip cost, and testability? To better understand which memory best suits your design, it is wise to explore the availability and trade-offs of the various NVM types for fully integrated SoCs. (For more detail on the bit-cell differences among the various NVM technologies, see "NVM-technology overview.")
Memory options
A hypothetical RF-receiver system serves as a vehicle for comparing the various memory options (Figure 1). A brief orientation reveals several strategic opportunities for embedded NVM. At the front end, an analog signal enters a low-noise amplifier and then proceeds through a set of mixers, filters, and ADCs. In the digital path, the design application might suggest additional signal processing, including filtering, mixing, and demodulation, before the data ends up in the microprocessor. In the example, one path provides control, and the other path provides data. The microprocessor manipulates the data according to the application and delivers the information out the back end. So, what opportunities does NVM offer in each stage for enabling the system, improving performance, or simplifying design?
Opportunities exist throughout the design. For example, in the analog front end, small amounts of NVM ensure design accuracy in multiple places: gain adjustment for the low-noise amplifier, trim matching for the signal mixer, filter adjustments for the phase-lock loop, analog-filter coefficients, gain and phase adjustment, and manufacturing trim for the ADC. Process variations invariably alter the characteristics of analog components.
The ability to change parameters through NVM storage allows designers to ensure that their circuits operate correctly. Furthermore, temperature changes affect analog-circuit operation. For circuitry operating under conditions of wide temperature swings, the addition of MTP (multiple-times-programmable) NVM or a parameter look-up table based in OTP arms designers with the ability to maintain accuracy of their design in the field.
The larger bus widths asSoCiated with a digital back end typically require larger amounts of NVM. The DSP block might require filter-coefficient and demodulation-parameter storage. Once the data enters the microprocessor block, the application might call for decrypting information using frequently changing keys, performing frame synchronization, or storing small code updates. Each of these data requirements varies in when and how often they update, their size requirements, and why the updates occur. Table 1 provides a summary of the hypothetical system-parameter-storage require-ments.
If designers split their memory requirements into three categories of less than 4kbits, as much as 256kbits, and more than 256kbits, they can go ahead and partition the system accordingly. But they may further subdivide the memory choices into those programmed during manufacturing and those requiring updates over the life of the chip. Designers may divide this mixed-signal system into two chips (Figure 2). The front end tends to require less NVM and more OTP NVM. The digital back end, with the associated wider data buses, requires greater amounts of mostly MTP NVM. If an application needs access to more NVM - for example, for large code or data updates - designers may want to provide an interface to external NVM.
If designers must increase system integration, lower cost, and maintain scalability to smaller processes, what options are available? To answer that question, first examine an overview of embeddable NVM characteristics across process types (Table 2). (This comparison includes neither ferroelectric RAM nor magnetic RAM.)
Designers can then take a couple of approaches. One method continues the two-chip approach in which designers optimize the design of each piece. Designers may want to use fuse or antifuse OTP NVM for the small amounts of memory in the analog front end. In this case, designers achieve higher program speed than they would using logic OTP CMOS at the expense of higher power consumption. If the design is destined for high production volume, higher program speeds might be an important cost consideration. However, if the design requires field testing and programmability, the only choice is logic OTP CMOS; fuse or antifuse designs require factory programming.
Precision parts
Package characteristics can also affect precision analog parts. Postpackage programming might be desirable over wafer sorting, again indicating logic CMOS as the only choice. In either case, manufacturers develop the chips in leading-edge processes, and they require no extra mask charges, which lowers overall cost by yield and increases reliability. (Any additional masking layers affect all transistors in the circuit, because the extra processing steps introduce defects, resulting in lower yield and reduced reliability.)
For the digital back end, designers usually go with embedded EEPROM or Flash because that course is a straightforward transition from external memory. Embedded EEPROM and Flash come with the advantages that both control and data interfaces are already in place. Assuming that designers have a similar architecture for the embedded version, many choices exist. Bringing data storage on-chip also reduces the amount of I/O circuitry. It also allows designers to reduce system bill-of-materials cost by removing external components, lowers board costs because there are fewer lines to route, achieves fast read, and lowers power at the expense of extra process steps.
However, if your company determines that six to 10 extra process steps to bring EEPROM and Flash on-chip will too greatly impact the bottom line, then it is back to the drawing board. A quest for reduced power consumption and less of a processing hit might compel designers to use SONOS (silicon-oxide-nitride-oxide-silicon) Flash, which requires only about three extra masks.
A second approach is for designers to integrate the memory in a single mixed-signal chip. For the OTP NVM, either option works unless the design calls for field programmability or testability. If this situation arises, the only choice is logic NVM. For the digital portion, using SONOS Flash provides designers with a lower power, faster program option than embedded EEPROM. Selecting logic NVM for the midsized-memory requirements in the digital back end will cost you area and speed but will lower cost and typically increase yield. Now, the entire design fits into one process - generic logic CMOS - and requires no added process steps. Using generic logic CMOS provides designers with the additional advantages of leading-edge-process availability, design portability, and a lower power design. The only trade-off of this option is the limitation on memory size.
If the microprocessor requires an MTP memory on the order of multiple megabits, for example, size constraints limit the choice to EEPROM or Flash. Table 3 summarizes the primary design trade-offs.
Support-circuitry overhead
Another aspect designers should consider is support-circuitry overhead. All memories require operational control signals and decoding circuits, with complexity varying according to memory architecture. In the absence of external high-voltage lines, higher programming voltage requirements must have either on- or off-chip charge pumps. Designs that require greater memory endurance may require error-correction coding and some degree of cell redundancy. Depending on the erasure method the device uses, designers may need to use additional control circuitry to prevent overerase problems, such as stuck bits. Some designers may choose to use drop-in memory IP (intellectual property) from an IP vendor, which gives designers visibility into only the periphery of the memory. Designers care about the overhead because the selection of a type of NVM from a specific vendor impacts not only the chip design, but also the design and cost of the board it occupies. Table 4 summarizes a few peripheral-support-circuitry considerations.
Moving from external NVM to an internal embedded approach provides many benefits: increased design accuracy, lower board costs, decreased board complexity, greater testability, the ability to correct design errors, field programmability, and increased security. If designers can fit the design into a generic logic-CMOS process using careful design partitioning, their design will gain additional benefits, including lower power consumption, lower chip costs, and the availability of both OTP and MTP NVM from a single IP supplier.
Designers should first consider the type and size of NVM their design needs. Once they understand the NVM requirements, they can then evaluate requirements for read speed, design portability, field programmability, power consumption, and design area versus cost. Armed with this information, designers can pick the best IP supplier for the application at hand. Understanding the NVM options could mean the difference between a design that works and a design that works but soon fails in the marketplace.
Floating-gate FETs
For MTP (multiple-times-programmable) logic-CMOS floating-gate technology, a group of floating-gate FETs stores the charge (Figure E). Designers can implement the cell using a standard CMOS process without extra masks or process steps. During programming, pulling the N well of the tunnel PFET to high voltage while keeping the control gate at ground causes FN (Fowler-Nordheim) tunneling, erasing the floating-gate charge. Pulling the control gate to a high voltage while keeping the rest of the nodes at ground uses FN tunneling in the reverse direction to add charge to the gate. Hot carrier injection from the stress node can also program a cell. To read, external circuitry enables the read MOSFET using the select node and determines the current flow through a sense amplifier connected to the sense node.
Charge stored on a floating-gate FET with double polyfuse is the storage mechanism for embedded EEPROM or Flash (Figure F). To program, pulling the stress/bit node to a high voltage while keeping the select at ground or at a negative voltage creates FN tunneling, which erases the floating-gate charge. Pulling select to a high voltage while keeping the rest of the nodes at ground uses FN tunneling in the reverse direction to add charge to the floating gate. Hot carrier injection from the stress/bit node can also program the cell. To read, external circuitry uses the select node to enable the cell and determines current flow through a sense amplifier connected to the sense node.
SONOS embedded Flash memory works in the same way as the floating-gate Flash but replaces the floating gate with a layer of nitride as a charge-trapping medium. SONOS is generally thinner than floating-gate NVM, enabling programming and erasing at lower voltages. The thinner oxide simplifies the process steps to only two to three extra layers from the CMOS baseline process rather than the six to 10 layers for floating-gate NVMs
.NVM-technology overview
Today, most embedded NVMs (nonvolatile memories) store information by changing the conductance of the read path in a bit cell. Memory designers use two principal methods to modify read-path resistance: a polyfuse/oxide-antifuse element or modification of the threshold of a MOSFET through charge storage.
Designers typically measure process complexity by assessing how many extra mask steps over logic CMOS they will need to implement the embedded NVM. (Any additional masking layers affect all transistors in the circuit, reducing yield due to the added defects the extra processing steps induce.) Designers must choose among NVMs requiring no added masks, such as logic-CMOS NVM, including polyfuse; two to four additional masks, such as SONOS (silicon-oxide-nitride-oxide silicon); and six to 10 additional masks, such as embedded Flash. Embedded Flash usually requires a second and sometimes a third polysilicon layer. Figure A provides an example of a generic NVM cell. For a silicided polyelectrical fuse, the storage device is a polyresistor (Figure B). When designers program the device, a current of approximately 10mA that passes through the "stress/bit" node causes self-heating and electromigration of the silicide and increases the resistance of a narrow section of polyfuse on the field oxide.
To read the bit value, external circuitry enables the MOSFET using the "select" node, and then a sense amplifier connected to the "sense" node detects the state. Increased resistance in the read path indicates a change of storage state. But polyfuse circuitry has limitations, including OTP (one-time-programmability) limitations, relatively large cells due to the large programming current, and some reliability concerns over fuse regrowth. For an electrical antifuse, the storage device is an oxide capacitor (Figure C). When designers program the device, applying a large voltage at the stress/bit node ruptures the oxide.
To read, external circuitry enables the MOSFET using the select node, and then a sense amplifier connected to the sense node detects the state. Reduced resistance in the read path indicates a change of the storage state. The limitations of oxide-antifuse circuitry include OTP problems, some reliability concerns about oxide breakdown, and scalability concerns for advanced processes. (Oxide breakdown is not well-defined for ultrathin oxides.) Most EEPROM and Flash products use floating-gate technology.
Figure D shows a floating-gate PFET. The select transistor can be either an NFET or a PFET. The floating FET comes out of fabrication uncharged or may be erased with ultraviolet light, leaving the gate in the off position. Charge injected onto the floating gate from the stress/bit node using hot carrier injection turns on the floating-gate FET. To read, external circuitry enables the MOSFET (select node), and then a sense amplifier connected to the sense node detects the state through the presence or absence of current flow.
