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New design infrastructure by Hitachi and Cadence doubles design efficiency

(Business News, 10 Apr 2007 )

Hitachi, Ltd. and Cadence Design Systems, Inc. have announced that, as of April 2, 2007, Hitachi has started operating its new design center aimed at enhancing design efficiency and reducing the design-cycle time for Hitachi's hardware products as part of its focus on the company's manufacturing capability. The design infrastructure, which has been co-developed by Hitachi and Cadence, will be used for large-scale-integration (LSI) and printed-circuit-board (PCB) designs.

With the advent of the new design infrastructure, Hitachi will strengthen its design and manufacturing capability and that of its group companies. Hitachi plans to centrally manage this design infrastructure from the newly established Hitachi Design Center in Yokohama, Japan, and plans to deploy it across all Hitachi business units and group companies via Hitachi's internal network. The Information and Telecommunications Systems Group is the first to adopt the new design infrastructure to design its core products, including servers, storage, routers and networking systems. In earlier evaluations of the co-developed Cadence and Hitachi design infrastructure, Hitachi succeeded in doubling the design efficiency and reducing design-cycle time by 40 percent.

Hitachi has been focusing on enhancing its manufacturing competency in terms of cost, technology, and quality to increase its competitive position in the industry. The implementation of the new design infrastructure is part of laying the groundwork to reform its design and manufacturing capability and then apply it across the entire Hitachi Group. Improving manufacturing in its hardware business divisions is based on the need to strengthen LSI and PCB design capability to develop competitive next-generation hardware platforms.

The new design system is entirely standardized on Cadence design technology, including high-level logic description language; logic verification with hardware acceleration; quality logic synthesis, which impacts chip speed; and distributed high-speed layout processing using multi-threading.

Hitachi, Ltd
Cadence Design Systems

 
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