Synopsys’ latest release of its Design Compiler synthesis solution, Design Compiler 2007, extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, boosting designers productivity and IC performance.
Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle. Moreover, topographical technology supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.
"Using topographical technology, the performance predictions made by synthesis correlated within 5 percent of physical implementation results," said Huang Tao, design manager at Hisilicon. "Design Compiler 2007 additionally reduced chip area by an average of 5 percent while meeting the aggressive performance targets of our telecom designs. Superior performance complemented by tight correlation to layout is exactly what our designers need to bring competitive products to market faster."
Topographical technology delivers tight correlation between performance results seen during synthesis and what is achieved after layout. This eliminates the need for time-consuming iterations between RTL synthesis and physical layout to achieve design closure. Design Compiler shares technologies and infrastructure with the Galaxy Design Platform physical design solution to deliver a consistent and highly predictable RTL-to-GDSII path.
"We were faced with conflicting test goals at Cypress: we needed high test coverage but with very few dedicated test pins and limited memory on our legacy testers," said Don Smith, design director for the Data Communication Division at Cypress. "We evaluated Synopsys' adaptive-scan test compression technology, which took less than a day to adopt in our flow. Based on the results we've seen, we are confident that we can deliver the highest quality products while leveraging our existing test equipment infrastructure."
Design Compiler 2007 includes several innovative synthesis technologies such as adaptive retiming and power-driven clock gating, to deliver an average 8 percent higher performance, 4 percent smaller area and 5 percent lower power consumption compared to the previous release. In addition, the Synopsys Formality equivalence checking solution has been enhanced to independently and thoroughly verify these technologies, thereby allowing designers to achieve higher performance without sacrificing verification.
Synopsys, Inc
