Some time ago a panel meet on 65nm technology for mixed-signal designs was attractively titled “Life begins at 65—especially for mixed signals.” The theme of this title contrasts with an idea making the rounds in the industry: that 65nm CMOS could be the end of the road for designs, and designers will have to look for CMOS alternatives.
For one thing, analog designers still implement most designs at 0.5 to 0.25 micron, and are not rushing into ultra-deep nanometrics, unlike digital designers. There are three main reasons for this. First, while digital functionality increases with the number of transistors and speed, analog functionality does not necessarily do so. Indeed, scaling may deteriorate performance due to noise and mismatch constraints. With today’s applications critical accuracy requirements, such performance deterioration is unacceptable. Second, the reduced power supply voltage makes it difficult to implement circuit techniques such as cascading and device stacking. The increased process parameter variability also affects analog circuit performance.
Analog designs are manual
Third, most analog designs continue to be done manually, with little supporting facilities. This makes analog design cycle long and error-prone, requiring frequent reruns, which is not conducive to shortening product time-to-market. Analog designers have always been limited by inadequate analog tools for boosting productivity or automating tasks. While recently commercial CAD-tool support for analog cell-level circuit and layout synthesis is emerging, enabling the designer to take the basic level of design abstraction for analog circuits beyond the transistor level, the gap between design tools available and required is increasing not only for analog but also for digital.
Analog occupies only a small fraction of the total area of mixed-signal ICs and SoCs. However, analog can be an impediment in terms of design time, effort, and cost. It is already a major reason for design errors and costly reruns.
In other words, beginning life at 65nm has been problematic. However, a definitive beginning has been made. Infineon claims it has built an analog device at 65nm. Some vendors, having successfully implemented ADC at 90nm, are working on 65nm devices. Consumer applications, especially in telecom and multimedia, increasingly demand mixed-signal designs, wherein high-performance analog and RF front-ends are embedded on the same chip as digital circuitry. These highly integrated solutions with demanding specifications have to be made at low-cost, which further complicates matters by making it necessary to avoid reruns.
I think the decisive factor in deciding whether CMOS design road ends at 65nm or life begins at 65nm will be the signal integrity issue, which involves verifying unwanted signal interactions through crosstalk or capacitive/inductive couplings resulting in parametric malfunctioning of the chip. Perhaps no single factor is as destructive of analog/RF circuitry performance as the parasitic signals generated by crosstalk or coupling. Signal integrity analysis is the key to boost analog design productivity. Of late designers have been giving more attention to analyzing digital switching noise. During switching operation, the digital circuit can inject spikes into the substrate shared by analog and digital circuits. The spike diffuses through the substrate, and is picked up by the analog circuitry, where it can create havoc with the genuine signals.
Noise distribution
The finite difference methods or the boundary element methods are currently used to examine the potential distribution of noise in the substrate. However, designers have to go a long way before techniques are developed that can accurately analyze the impact of unwanted signals on the embedded analog circuitry. This is just the beginning. Beyond 65nm deeper into ultra-deep nanometrics, designers will face even more signal integrity problems needing analysis and modeling, especially those arising due to EMC/EMI and electromagnetic interactions.
So, I believe, it is still not clear whether life begins at 65nm or CMOS roadmap ends at 65nm.
