New generation of CCM PFC controller with BiCMOS technology

ICE2PCS01/02 are the 2nd generation of Continuous Conduction Mode (CCM) PFC controllers, which employ BiCMOS technology. Compared to the 1st generation of ICE1PCS01/02, the new ICs have lower internal reference trimmed at 3V to ensure precise protection and control level. They also have other advantages such as wider Vcc operating range, improved internal oscillator and additional direct bulk capacitor over-voltage protection.

The pin-outs of ICE2PCS01/02 remain the same as those of ICE1PCS01/02 (Figure 1). Most Pins of ICE2PCS01 and ICE2PCS02 are the same except Pin 4. In ICE2PCS01, Pin 4 is to set the switching frequency. However, for ICE1PCS02, Pin 4 is for AC brown out detection.

The ICs are designed for converters in boost topology, and require few external components. Both current and voltage loop compensation are done externally to allow full user control. The typical application circuits of ICE2PCS01/02 are shown in Figure 2 and Figure 3 respectively, which are also the same as those of ICE1PCS01/02.

Major features comparison between ICE1PCSXX and ICE2PCSXX

IC supply voltage
Due to the new BiCMOS technology, the IC supply voltage operating range is extended from 10~21V (ICE1PCS01/02) to 11~26V (ICE2PCS01/02). The IC on threshold voltage is 1V up from 11V (ICE1PCS01/02) to 12V (ICE2PCS01/02).

There are two stages during IC turned on. First Vcc capacitor is charged from 0 to 7V, the IC internal regulator block starts to reset voltage at all external pins. The reset process will take about 10us. And then when Vcc voltage is charged to Vcc_on threshold, IC starts the soft start with gate switching. In the case of Vcc decoupling capacitance is too low such as 0.1uF, Vcc voltage may be charged up too fast and the time interval from Vcc=7V to Vcc_on is less than the reset time. Then the IC will not go through a proper soft start as the voltages at IC pins are not yet properly reset. To avoid such a problem, the delay circuitry is needed.

Figure 4 is a typical circuitry to supply PFC controller. Q2 is NPN transistor and controlled by external “Power on” signal. When “Power on” signal is “high”, Q2 is turned on provides base current for Q1. Q1 is turned on accordingly to supply auxiliary power to IC Vcc. The reset delay time is adjustable by changing the RC time constant of R1, R2 and Cdelay. The recommended values are shown in Figure 4 as 10kW, 10kW and 0.47uF respectively.

The same reset process also happens during IC power down when Vcc is discharged from Vcc_off to 7V. The reset time for power down is around 200us. Because IC is in power down mode with very low current consumption, typically 300uA only, the required Vcc capacitance for power down reset can be calculated as:


So the common Vcc decoupling capacitance 0.1uF is enough for reset delay requirement.

IC gate output
The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection. The maximum voltage at GATE Pin is typically clamped at 15V at high state. With the new BiCMOS technology, GATE low state voltage is reduced from 2V maximum (ICE1PCS01/02) to 1V maximum (ICE2PCS01/02). Due to the lower GATE low state voltage, the external MOSFET can be switched-off much faster and switched-off loss is reduced for higher efficiency.

Internal oscillator
With the new BiCMOS technology, the internal oscillator can be accurately adjusted without any noise interference. For ICE2PCS02, the switching frequency is fixed internally at 65kHz typical. For ICE2PCS01, the switching frequency can be adjusted by external resistance at FREQ Pin. The typical curve for switching frequency Vs Rfreq resistance is shown in Figure 5.

Bulk capacitor voltage sensing and over-voltage protection
The voltage at the bulk capacitor (Vout in Figures 2 and 3) is sensed by a resistance divider at Vsense Pin. The Vsense voltage is sent to error amplifier and compared with internal reference for voltage loop regulation. The internal reference voltage is 5V for ICE1PCS01/02, and 3V for ICE2PCS01/02. Due to different internal reference voltage, different resistance divider needs to be applied for ICE1PCS01/02 and ICE2PCS01/02 solution.

The Vsense voltage is also used for enhance dynamic response block. The thresholds to trigger enhance dynamic block in ICE2PCS01/02 are remaining as the same ratio as +/-5% of internal reference voltage, but the absolute value is implemented as 3.15 and 2.85V respectively.

In the case of Vout overshoots above +5% of nominal value, the enhance dynamic response block can fast reduce the duty cycle until zero. This function can be considered as Vout overvoltage protection. Besides the enhance dynamic block, ICE2PCS01/02 provides an additional OVP protection by directly shutting down gate output if Vout overshoots exceeds +8% of nominal value. In addition to enhance dynamic block, the directly OVP shut down function further improve the system reliability.

Current loop and voltage loop regulation
The basic operating concept of ICE2PCS01/02 is the same as ICE1PCS01/02. The ICs operate with a cascaded control: the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. The outer voltage loop controls the Vout and regulate the amplitude of the average input current.

The calculation of current loop and voltage loop compensation in Reference [3] is also applicable to ICE2PCS01/02. However, with the new technology, some internal constants are changed as below. With the parameter changes, both current loop and voltage loop compensation need to be adjusted accordingly.
Control loop parameters comparison

For the current loop,



In the case of switching frequency 65kHz, fave is chosen to be 10kHz, assuming M1 at 0.935, then the necessary Cicomp is:



So the practical Cicomp will be 4.7nF or even higher.

Summary of major changes
Table 3 lists all the major changes in ICE2PCS01/02 and the corresponding advantages over ICE1PCS01/02. It can be seen that some of the features have been significantly improved, which will lead to better application performance and more flexible designing.

PCB layout guide
In order to avoid crosstalk on the board between power and signal path, and to keep the IC GND pin as “clean” from noise as possible, the PCB layout for GND must be taken care of properly. Below are some suggestions for GND connection and Figure 7 below illustrates as a good example.
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Star connection rule for main power stage GND: the PCB tracks of MOSFET source, output load GND, IC auxiliary supply GND and shunt resistor are separated and connected together at bulk capacitor negative Pin.

Star connection rule for small signal IC GND: the IC external components which need to be connected to the small signal GND bus highlighted in red color. Such GND bus is connected to IC GND Pin.

Connection between main power stage GND and small signal IC GND: in Figure 6, a single PCB track in pink color directly connect IC GND pin to power stage star connection point - bulk capacitor negative. This is to ensure that the voltage between IC Isense Pin and IC GND Pin does not observe the switching rectangular noise current. The dark green and blue tracks denote for flowing paths of high frequency rectangular switching current.

Vcc decoupling capacitor Cvcc: the decoupling capacitor need to be placed close to IC Vcc and GND Pins as much as possible. The GND track of Cvcc (green color in Figure 6) should be connected at the point on the single PCB track connecting between IC GND Pin and power GND point so that the large gate charging current will not pass through the small signal GND bus.

Vsense capacitor Cvsense: to reduce noise in Vsense Pin, small capacitor up to 0.1uF can be added between Vsense Pin and small signal GND bus.



References:

[1] Infineon Technologies: ICE2PCS01 - Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM); Preliminary datasheet; Infineon Technologies; ICE2PCSXX, Jan, 2007.

[2] Infineon Technologies: ICE2PCS02 - Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM); Preliminary datasheet; Infineon Technologies, Jan, 2007.

[3] Luo Junyang, Liu Jian Wei, Jeoh Meng Kiat, ICE1PCS01 Based Boost Type CCM PFC Design Guide  Control Loop Modeling, application note, Infineon Technologies, Feb, 2007

Illustrations:

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Table 1

Table 2

Table 3