The CEVA-TeakLite-III is a third-generation DSP architecture based on the broadly adopted TeakLite family of DSP cores. This feature-rich native 32-bit architecture is backward compatible with previous versions of CEVA-TeakLite cores and delivers higher performance and lower power for demanding applications such as 3G cellular handsets, High Definition (HD) audio, Voice-over-IP (VoIP) and portable audio devices.
For the first time, a DSP compatible with the CEVA-TeakLite architecture delivers native 32-bit processing, which includes a 32 x 32 MAC unit to provide efficient support of advanced audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD, DTS-HD and more. The architecture also features a 10-stage pipeline, enabling the core to reach operating speeds of up to 425MHz in a 65nm process (worst-case conditions and process). Compared to CEVA-TeakLite, initial performance estimates show it to be up to 4 times faster on basic operations and 2 times better on most popular audio codecs.
CEVA-TeakLite-III builds on the architecture of CEVA-TeakLite-II, CEVA-TeakLite, and CEVA-Oak, the most established and successful licensable DSP architecture to date. The CEVA-TeakLite family has been licensed to over 50 partners worldwide and has shipped in over 750 million devices. CEVA-TeakLite-III is fully compatible to CEVA-TeakLite and CEVA-Oak architectures, allowing its users to leverage both existing applications and the large software installed base already available from CEVA and the CEVAnet™ third-party development community.
The flexible CEVA-TeakLite-III architecture is available in various configurations, each specifically tailored for particular applications and system architectures. CEVA-TL3210 and CEVA-TL3214 are two specific configurations of the architecture, available for licensing today. CEVA-TL3210 includes a mix of tightly coupled memories and direct mapped caches, and allows easy SoC integration using AHB bus protocols. CEVA-TL3214 targets cost sensitive SoCs based on a TeakLite-compatible X/Y data structure and minimizes SoC integration investments. An additional configuration, the CEVA-TL3211, includes an advanced 2-level cached memory subsystem equipped with a memory protection unit and AXI system interfaces. This configuration targets single-core embedded applications and will be available for licensing in early 2008.
CEVA, Inc
