New chip material addresses power leakage, scaling for 45-nm and beyond

Texas Instruments Incorporated has announced plans to integrate a “high-k” value material within the transistors in its most advanced, high performance 45-nanometer (nm) chip products. For years, high-k dielectrics have been under consideration to address leakage, or power drain, which has become increasingly problematic as transistor dimensions continue to shrink. Through its approach, TI will reduce leakage by more than 30 times per unit area as compared with commonly used silicon oxide (SiO2) gate dielectrics. In addition, TI’s high-k choice offers the compatibility, reliability and scalability to continue delivery of high volume, high performance and low power semiconductor solutions through the 45-nm and 32-nm process nodes.

TI’s 45-nm Process
Last June, TI unveiled details of its 45-nm process that will double output per wafer through use of 193-nm immersion lithography. Through a number of techniques TI will also achieve a 30 percent increase in performance of its SoC processors, while reducing power consumption 40 percent. TI expects to sample a 45-nm wireless product in 2007, with qualified production starting by the middle of 2008. High-k dielectrics will be added in later versions of the 45-nm process for TI's highest performance products.

Several 45-nm recipes address customers’ unique end-product requirements and provide options for creating flexible, optimized designs. These options includes a low power offering that extends battery life in portable products, while delivering the necessary performance for advanced multimedia functionality in tightly integrated SoC designs. A mid-range process supports TI DSPs and the high performance ASIC library for communications infrastructure products. The third, highest performance 45-nn process option supports MPU-class performance and is expected to be the first process to integrate the high-k material.

HfSiON Technical Overview
TI will leverage a chemical vapor deposition process (CVD) to deposit Hafnium Silicon Oxide (HfSiO) followed by reaction with a downstream nitrogen plasma to form HfSiON. While the benefits of Hafnium-based dielectrics have been widely recognized for the impact on leakage, implementation has previously presented several hurdles. Issues include electrical compatibility with standard CMOS processes, as well as challenges in matching the carrier mobility and threshold voltage stability that SiO2-based gate dielectrics have previously delivered. However, by implementing the nitrided CVD technique, TI is able to solve the leakage issue without degradation of the other key parameters that customers have come to expect from SiO2-based gate dielectrics. TI’s approach reduces leakage significantly over any of the SiO2-based material options.

The nitridation of CVD HfSiON film also delivers the scalability that supports the performance, power consumption and gate length requirements outlined through the 32-nm node. Through a modular addition to the typical CMOS gate stack process, HfSiON integration has been demonstrated offering mobility that is 90% of the silicon dioxide universal mobility curve, with effective oxide thicknesses (EOTs) below 1-nm. These results were accomplished without sacrificing reliability or adding significant cost to the CMOS process. Precise tuning of the film composition, tight controls, and high throughput also make HfSiON suitable for high volume manufacturing.

TI’s extensive research includes the composition, process optimization and characterization of HfSiON gate dielectric films. In addition, TI’s efforts are fully compatible with its 45-nm metal gate strategy.

Texas Instruments