TD-SCDMA Digital Front End reference design solution

Xilinx, Inc., in partnership with Multiple Access Communications (MAC) Ltd, have announced the immediate availability of a TD-SCDMA Digital Front End (DFE) reference design solution based on the Xilinx System Generator for DSP tool. The new reference design solution significantly reduces the development time required for the complex digital algorithms found in TD-SCDMA DFE radio applications. Consisting of example reference designs, full-speed working demo and complete IP library that includes optimised System Generator IP Blocks for digital up conversion (DUC) and digital down conversion (DDC) functions, the TD-SCDMA DFE reference design solution enables users to construct 3GPP-compliant DFE designs for a wide variety of base station configurations.

The TD-SCDMA DFE reference design solution enables developers to reduce design risk and provides a quick time-to-market route from concept-to-production for digital radio applications. The IP library encapsulates the signal processing functions that determine compliance with the 3GPP requirements in such a way that complexity of these functions is hidden from the library user. With this approach, developers can save many man-months of algorithm development and many man-years of hardware development time given the multiple antenna and carrier configurations, ranging for single carrier-single antenna to 6 carriers-8 antennas per sector.

About the Xilinx TD-SCDMA DFE Reference Design Solution
The TD-SCDMA DFE reference design solution is enabled by Xilinx high-performance Virtex -4 platform FPGAs, which offer superior performance and cost-effective DSP processing capability, enabling a lower cost-per-channel than competing solutions. In addition, Virtex platform FPGAs allow in-field upgrades which make the base station more adaptable to evolving technologies and standards.

“The market is looking for flexible, cost-effective solutions which can be developed from concept-to-production as quickly and easily as possible,” said David Kenyon, managing director of MAC Ltd. “The combination of the Xilinx Virtex platform FPGA and Mac Ltd’s proven expertise in developing wireless signal processing solutions has allowed us to develop a TD-SCDMA DFE reference design that uses FPGA resources very efficiently and fits into very cost-effective devices.”

The TD-SCDMA DFE reference design supports up to six carriers per antenna and offers a flexible intermediate frequency input or output. DUC performance highlights are an EVM of 1.6% RMS and Adjacent Channel Leakage Ratio (ACLR) >80dB, for an occupied bandwidth of >99.9%. The DDC block provides Adjacent Channel Selectivity (ACS) > 75dB, blocking >80dB and a low latency Signal Path Delay of just 14.9us.

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