Synopsys’ latest release of its Design Compiler synthesis solution, Design Compiler 2007, extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, boosting designers productivity and IC performance. Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle. It also supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.
Design Compiler 2007 includes several synthesis technologies such as adaptive retiming and power-driven clock gating, to deliver an average 8 percent higher performance, 4 percent smaller area and 5 percent lower power consumption compared to the previous release.
Synopsys, Inc., www.synopsys.com
