With TSMC set to manufacture chips at 45nm from next month, it seems the transition from 65nm to 45nm has not been as disruptive as thought earlier. True, designers have to cope with longer design cycles, increased tape-out costs, and higher abstraction levels. Yet, the advent to 45nm has been fairly smooth and the processes at the two nodes have been much the same, both from perspectives of process engineers and designers, even as TSMC confirms that the era when process migration implicitly meant higher performance without design and circuit changes is behind us.
TSMC informs that on the process side 45nm node presents two major changes compared to 65nm node: the new node introduces immersion lithography for critical layers, and lower-k porous material for inter-metal dielectric. The lower-k material offered the biggest challenge. More fragile than low-k materials used hitherto, it necessitated changes in design rules to make design more robust. Being more porous, it is greatly vulnerable to contamination, which can lead to higher effective k, and in worst case, dielectric failure. TSMC took care of these problems through enhanced sealing layer techniques, which, however, increased conductor effective cross-section, necessitating more design changes.
TEMPERATURE INVERSION
A new phenomenon seen is called temperature-inversion. Herein, the worst-case delay for a circuit could actually occur at low-temperature corner rather than the high-temperature one. All the new issues can generally be taken care of within process engineering or library development and the designer is insulated from them. However, TSMC cautions, not every time this has worked.
TSMC 45nm DFM initiative has gone beyond traditionally supplied design rules and SPICE models. It provides additional manufacturing data essential for achieving high yields in deep nanometrics. Both model-based and rule-based approaches are available for designer implementation, with a DFM Data Kit for third-party EDA tools, and a TSMC DFM toolkit with advisories and utilities.
SRAM stability was an important concern. When geometries shrink, SRAM read and write margins decline with decreasing operating voltage. Read margin mainly measures cell stability during a read operation, while write margin, the ease with which a cell can be written. Lack of balance in either margin results in a cell that can’t retain data or can’t alter data. Many novel ideas have been proposed to tackle this problem. One idea is to dynamically manipulate bias levels to manage the balance between read and write margins in a SRAM array. Another is adjustment of the read and write margins on the basis of how memory array is used. The idea of manipulating electrical characteristics of a circuit based on its current function, though fascinating, has not yet been tested.
TSMC chose to use the conventional six-transistor SRAM and eight-transistor dual-port cells. This seems to be working. However, the Company cautions design engineers about IR drop and switching noise with reduced supply voltage.
Yet another area of concern was analog. TSMC claims that using thick-oxide transistors and proper disciplines for isolation techniques gives good results on analog circuits.
COPPER RESISTIVITY
Copper resistivity continues to remain a challenge. Below 90nm linewidths, copper resistivity rises rapidly because of increased electron scattering on grain boundaries and interfaces. This rise can reduce or even wipe out the capacitance benefits of low-k dielectric materials. The likely solution to this problem is to create a combination of materials, along with process and design changes.
Experts have offered two possible process fixes to reduce resistivity effects: first, minimize the volume that diffusion barriers occupy by making them ultra-thin; and second, enlarge copper grains to diminish boundaries and encourage unimpeded electron flow. Some experts have opined that the solution should come in the form of short lines and a move to three-dimensional interconnect.
For 45nm node, copper resistivity still seems fixable; but probably it is at the end of its utility.
