Cadence Design Systems has announced that they have extended their design chain alliance to deliver further benefits to their mutual customers. The result is the Cadence Optimization Methodology Kit for ARM Processors, which helps design team enhanced performance, power utilization, and area when hardening synthesizable ARM processors. This phase builds on the companies' existing collaborations on digital IC design, power management and verification to provide new solutions for application-specific needs.
The goal of the Cadence Kits approach is to simplify the application of Cadence technology and so shorten time-to-productivity. Customers can then focus their precious design resources on design differentiation rather than design infrastructure. Cadence Kits address application-specific design challenges by combining a verified methodology, packaged in platform flows, with IP and consulting all demonstrated on a representative reference design.
The Cadence Optimization Methodology Kit for ARM Processors builds on the success of the silicon-proven ARM-Cadence Encounter(R) Reference Methodology. In addition to the reference methodology, the kit includes Cadence Encounter RTL Compiler synthesis, First Encounter(R) silicon virtual prototyping, front-end views for the ARM Artisan(R) SAGE-X(TM) standard cell libraries for TSMC's 0.13-micron and 90-nanometer G processes, and service and support to help designers achieve high performance, low power and small area levels, while reducing development time.
As two founding members of the Silicon Design Chain Initiative, ARM and Cadence have collaborated on solutions to reduce risks and design time for their customers. For example, the companies have already delivered:
• Low-power design techniques demonstrated to reduce power by more than 40 percent on a 90-nanometer test design.
• Accelerated SoC emulation by integrating the Cadence Incisive(R) functional verification platform and the ARM Integrator(TM) Logic Tile products.
• The ARM-Cadence Reference Methodology, which enables predictable performance, power and area results.
"At Oki, we have seen substantial power and area savings using Encounter RTL Compiler on our designs based on our uPLAT SoC System LSI Design Platform, which features the ARM946E-S(TM) processor," said Masakazu Urahama, manager of the Silicon Platform Design Department, LSI Design Division, at Oki Electric Industry Co.
This deepening relationship between ARM and Cadence will result in additional projects to ensure more optimized products from both companies are aligned to meet customer market requirements. Areas of collaboration include extending the companies' continuing work in advanced processor cores, system verification, and on extending the effective current source delay model (ECSM) which Cadence pioneered. The companies will expand work done through the Silicon Design Chain Initiative to add additional low-power design capabilities, and also extend support for system languages, including the e, SystemC, and SystemVerilog languages.
Availability
The Cadence Optimization Methodology Kit for ARM Processors will be available in October 2005.
