Following a tough year of flat growth, the electronic design automation (EDA) industry is taking some needed R&R before cautiously launching into 2006.
Gary Smith, chief EDA analyst at market research firm Gartner Inc., is moderately hopeful about 2006, predicting a 7.9% rise in EDA tool sales to $4.3 billion. In 2005, EDA software stayed virtually flat at $3.96 billion, from $3.94 billion in 2004.
Erach Desai, independent financial analyst and business consultant, agrees with Smith’s assessment. “If you look at total revenue for the public EDA companies for the quarters reported in calendar year 2005, plus adding in the December calendar quarter guidance, what I show for pure EDA is that 2005 revenue compared to 2004 is down 0.4%,” he said.
Specifically, Desai calculates 2005 EDA revenue for public companies at $3.25 billion with 2004 revenue at $3.26 billion 2004, which was only up 1.1% over 2003. In 2006, he expects the growth rate to be below 5%, compared with Gartner’s 7.9%. By comparison, Desai’s semiconductor index was up 21%, and he expects2005 to register 8% to 10% growth.
“Fundamentally, the dynamic is interesting,” he noted. “Everyone knows that ASICs design starts have collapsed – they are not dead, just collapsed – and this has disproportionately impacted EDA.”
Why? With only two big competitors in the design implementation segment, pricing power has been lessened from lack of other competitors.
Further, Desai believes the industry is stagnant because large EDA deals are occurring at a lower annual rate than previously. Case in point: In the fall of 2002, number two EDA supplier Synopsys Inc. closed a $240 million deal with Intel, amounting to $120 million per year. When it renewed that deal in late 2004, it was for another two years, but at $200 million or $100 million per year. Again – the big deals are shrinking, he said.
The case has been the same for EDA market leader Cadence Design Systems Inc. The company’s biggest tool deal happened with IBM in the third quarter of 2002, concurrent with a separate agreement to purchase of IBM’s test business. The tool agreement was $130 million to $140 million for three years, equaling about $45 million per year. Then, in the third quarter of this year, Cadenced inked a three-year deal that totaled 22% of its revenue – speculated to be IBM again – for about $96 million or $32 million per year.
“The point is, if the largest, healthiest EDA customers are inking these smaller deals, why wouldn’t I believe the Toshibas, TIs and Fujitsus aren’t doing the same thing. TI has said it moved a lot of dollars away from Synopsys to Magma. The industry has to prove its value,” he offered.
It has been suggested that to pad their value to Wall Street, some EDA vendors have used “creative” methods of accounting that may include recognition of such non-GAAP revenue termed “financial backlog,” defined as, “future installments not yet due and payable under time-based licenses and maintenance contracts.”
However, Desai asserts, bookings and backlog aren’t going to cut it forever, and EDA vendors need to give hard dollars to really give a feel for where the health of the industry truly is.
In other parts of the semiconductor industry, these questionable but legal tactics don’t seem to occur. “I believe that when companies like TI, Cypress, Applied and Novellus talk about six-, nine- and 12-month shippable backlog, they report hard numbers every quarter,” he added.
Exactly what will drive EDA revenue growth is the burning question. In the past year, the buzz has been in two areas: at the front end, where it is all about electronic system level (ESL) advancements; and then at the back end of the design flow moving into manufacturing, the hope is in design for manufacturing (DFM).
Gartner’s Smith believes the growth in EDA tools in 2006 will be in the ES level segment that he predicts will grow 36 percent, while all other segments slow to a rate below 10%.
At the same time, “we seem to be figuring out DFM and everyone is now trying to make all the toolsets compliant. This is significant because it requires a complete retooling of the IC CAD market,” he noted.
“Many vendors claim to have DFM capabilities and customers are currently conducting benchmarks to see who is doing what. It appears that Mentor and Synopsys are the leaders in the DFM space with Cadence’s newest tools looking promising,” he continued.
From following the EDA industry over the past two decades, Smith is keenly aware of interesting dynamics that occur in this space, one of which is happening currently. As the next jump occurs in methodology – in this case, from the register transfer level method of designing chips to a manufacturing-aware process – general industry consolidation goes in reverse, with a flurry of spin-offs and startups emerging. Smith believes at least 30 such companies will appear just in the DFM and ES level space, with many coming out of Synopsys.
“DFM technology is almost reinventing the way we do silicon,” Smith concluded.
Desai disagrees with the overall industry significance of DFM. “DFM is a feature – like low-power or signal integrity – not an industry segment. If anything, ESL will steal the show,” he stated.
However, it is agreed that the turmoil happening in the IC CAD design flow has shifted sales away from the integrated IC implementation toolset – typically more price-laden than point tools – to the more traditional front-end (CAE) and back-end (CAD) design flow.
This dynamic may also help to explain why the largest deals at EDA companies have shrunk, as illustrated above. As the industry moves 65nm and below, commercial tools just do not cut it. While they might have any commercial software tool at their disposal, to stay on the cutting edge, the top semiconductor vendors keep the data required to build the best EDA tools in the utmost secrecy.
For an EDA tool to be worth its license price, it must do a better job of something than the customer could have done itself. Herein lays EDA’s biggest challenge: Maintain its momentum of technological innovation while still cozying up to its closest IC buddies in order to determine what its value could be to those companies.
This is where the ES level comes into play. With its potential to reach further into the enterprise than simply a chip design flow would, an executive from the industry’s leader, Cadence Design Systems Inc. explained that the ES level is capable of going where the EDA industry has not gone before.
“Complexity has bred specialization [in the design organization], in addition to interdependencies between design groups,” said Steve Glaser, VP of Cadence’s verification group.
As such, adopting an approach that automates business processes across functions gives a view into the organization from a process perspective. While this goes against the language-centric EDA approach, it reaches beyond what the industry has typically offered. Cadence looks at this in a multi-tier fashion with layers of functions built on top of a foundational technology layer, the whole structure it calls the “Enterprise Verification Stack.”
While this is just part of the puzzle that Cadence is working on, the key is to begin thinking beyond point tools that have run out of steam, to figuring out how to link in what the system engineering folks are doing back to the original spec—this is where the true value of working at the electronic system level becomes tangible, Glaser explained.
“If you can show how different levels within a design organization interconnect, it brings a larger value proposition at the enterprise level in terms of quality of results and predictability. The ability to have predictability into a crisis and predictability for multi-site projects is significant. At this level, you can talk about end product quality,” he said.
Cadence’s Enterprise tools contain components of all of the Enterprise Stack layers, and while it is not yet a 100 percent solution, it does move things a lot closer. So far, 50 to 60 customers have begun to adopt this methodology of using specification and planning to drive optimization, and even by coming in at a lower level they are seeing benefits, Glaser concluded.
