Accellera have organised a panel session at GSPx, in Santa Clara, California on Wednesday, 26th October, 2005. The event is scheduled from 0900 to 1000 hours local time and will be held at the Santa Clara Convention Center at Room 204.
About the event
Members of Accellera's working group will present how Accellera standards such as the Property Specification Language (PSL), also known as IEEE Std 1850, and the SystemVerilog Hardware Design and Verification Language (HDVL), also known as IEEE P1800, can be used to improve IP delivery and verification.
The problem of ensuring the quality and usability of IP for system designs is becoming a major concern for system integrators and IC manufacturers. This is particularly true for complex, highly configurable components such as DSPs. To solve this problem, the industry is turning to standards organizations such as Accellera to enhance standard design and verification languages to keep pace with the industry's need for advanced verification technology.
The use of assertions and formal techniques is a recognized path to dealing with these issues. The combination of assertion-based techniques with standard design languages is an effective way to bring this technology to the broad base of users who need it.
This panel discusses how these techniques are being adopted by IP designers to solve their verification and integration problems. It also discusses what additional work is needed to ensure interoperability between IP blocks that may have been designed by different groups or companies and may be using different languages and methodologies for design and verification.
Moderator: Victor Berman - Cadence Design
Panelists: Cesar Quiroz, CoWare; Cary Ussery, Improv Design; Kenneth Larsen, Mentor; Bassam Tabbara, Novas; Rich Faris, Real Intent; Tom Anderson, Synopsys
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