Productivity versus yield

It's all about productivity versus yield. Every discussion of the future of EDA boils down to the same conundrum: how to manufacture efficient chips without the need for time-wasting engineering tweaks. To make designers more productive as they work at 45 nanometers and beyond, the EDA vendors are touting future tools that will raise chip design above its current capabilities, allowing designers to manipulate blocks of circuitry as easily as they once manipulated individual components. To eliminate tweaks without affecting yield, EDA vendors intend to make their tools more aware of photomask and foundry processes. If both initiatives pan out, designers will have the best of both worlds: tools that are both easier to use and more effective when it's time to make the chip.

There's only one problem. No, two. First, as the semiconductor industry moves to 45 nm and beyond, it will become increasingly difficult to create an accurate model of manufacturing processes, making automated design for manufacturability (DFM) unlikely. Second, tools that raise the design process far above the current capabilities, rather than making designers more productive, may add complexities associated with system design to a process already overburdened with minutiae. If the EDA industry fails to address these problems, the increased complexity and expense of chip design may transform the basic economics of the semiconductor industry and greatly reduce the market for EDA tools.


"The problem with the EDA industry is that the problems have not become difficult fast enough to generate a lot of demand for existing methodologies."
—Wally Rhines, CEO, Mentor Graphics

The soft underbelly of chip design
It's a truism in physics that the smaller you go, the weirder things get, and that's certainly the case with chip design. As the industry has moved to ever smaller geometries, chip designs have been plagued by an increasing number and variety of parasitic electrical effects. Although physicists seem confident that it will be possible to manufacture chips at 45 nm and beyond, that miniaturization will come at a price. The smaller you go in chip manufacturing, the harder it gets to achieve acceptable yields.

A big part of the challenge is wavelength. Because the beam of light that generates a photomask is so much larger than a chip's components, photomask makers are forced to use increasingly complicated RET (reticle enhancement technology). But RET isn't a free ride. Each successive node brings a geometrically larger number of RET-mandated design rules. At 130 nm, the situation was manageable, with some 200 special rules. That number ballooned at 90 nm to some 2,000 rules. But as the industry looks forward to 45 nm and beyond, RET requirements (barring a complete revolution in photomask technology) may well turn chip design into a designer's worst nightmare.


Unfortunately for chip designers, RET-mandated design rules are highly interdependent and conditional. A rule that works at one location on a chip may not work the same at another, depending on the behavior of some third, or fourth or fifth rule. In other words, designing chips at 45 nm and beyond will be highly complex, burdened with a mind-boggling horde of complicated and inconsistent design rules.

Chip design used to be a "design it and throw it over the wall for synthesis" kind of business. However, the explosion of RET-mandated rules has transformed chip design into a collaborative effort between EDA vendors, design firms, photomask makers and foundries. "What most people are doing today is 'electronic design assistance,' not 'electronic design automation,'" complains Magma Design Automation CEO Rajeev Madhavan.

The EDA vendors do have strategies in place to address this problem. "As we move to new processes and materials, there will be a greater emphasis on yield," predicts Synopsys CTO Raul Camposano. "We expect major demand in the areas of design for yield and lithography for yield." However, although everybody agrees that DFM is a great idea, some design engineers are skeptical that EDA vendors can deliver as planned. "As we go to 45 nm, the greater quantity of submicron effects means that it will take longer for manufacturing processes to settle down and thus longer for the EDA vendors to build mature models," says Venkat Ghanta, a physical design manager at Cisco Systems. "With all the difficulties we expect with photomasks and RET, I can't help but think they'll be behind the curve."

Similarly, Texas Instrument's manager of EDA strategies, Mike Fazeli, expects that smaller geometries, rather than heralding a return to the good old days of "real" design automation, will instead require increasingly close partnerships throughout design and supply chains. "We'll need to continue to examine new relationships and new engagements in order to explore new territory and field-test new capabilities," he says. Although Fazeli characterizes himself as "more optimistic than most" when it comes to the potential automation of DFM, he concedes that the problems may be too much for the EDA vendors to handle. "It is quite possible that the automated solution isn't as simple as we thought, just like analog circuitry synthesis," he says.



"It is quite possible that the automated solution isn't as simple as we thought, just like analog circuitry synthesis."
—Mike Fazeli, manager of EDA strategies, Texas Instruments

This is not to say that designers believe that the EDA vendors are stumped. "The EDA segment can always come up with a solution, once a problem has been identified," insists Ghanta. In fact, it's well known in the engineering community that pesky parasitics could be neatly avoided through the use of highly conservative designs in which components aren't laid out close enough to create nuisance effects. However, the more conservative the design, the less benefit there is to moving to the next node.

In other words, without fully automated DFM, designers will inevitably end up spending more and more time with each chip design, in effect trading designer productivity for greater yield.

Abstract or just obtuse?
The obvious solution is to make chip designers more productive, which EDA vendors hope to accomplish by raising the design process to a higher level of abstraction. According to this theory, system-level tools such as SystemC will allow engineers to manipulate billions of components, try various theoretical chip designs, make trade-offs between silicon utilization and reliability and quickly generate a workable chip.

For example, Cadence Design Systems CTO Ted Vucurevich envisions automated tools that define and simulate chip designs, using a variety of target technologies, such as intellectual property (IP) blocks and programmable logic. "The thought is to move away from the issues of scaling, capacity, performance and closure and into a creative domain where designers can envision the end product rather than the circuitry behind it," he explains. "Such tools will allow designers to explore different architectures from the perspective of process and cost." Similarly, Synopsys believes that the future lies in reusable IP blocks, prequalified for manufacturing, that can simply be dropped into a chip design, according to Composano.

The idea that IP will play a major role in the future is responsible for many new firms' entering the market for semiconductor IP, making IP the fastest-growing segment of commercial EDA (see the "Worldwide EDA Revenues" chart, below). However, the idea of using IP as a vehicle for design automation may be a bit naive, according to Sanjay Srivastava, CEO of Denali Software, an EDA firm that specializes in IP. "Making IP work generally requires the active participation of the people who created it," he says. "Contrary to popular belief, IP is not a commodity."




Camposano agrees that in the real world, IP isn't always up to snuff. "If the code is sloppy and you have to go in and fix it, you might as well just rewrite it from scratch," he says. "The key to reusable IP is quality and standardization, which let it be quickly verified for use in any given chip design." To illustrate this point, Camposano cites the example of the C programming language, a de facto standard in the software world. "One of the reasons it works so well is that it's standardized," he says.

However, the triumph of C also presents an eloquent argument against the viability of IP as a vehicle for design automation. Three decades ago, software pundits were predicting that reusable code modules would replace traditional software coding and that the programmers of the future would mix and match plug-in software modules rather than create new applications. Despite all the grandiose automation schemes, however, most computer programs are still handcrafted, as evidenced by the success of C, which retains features dating back to the days of assembly language. Although it's true that Web services conventions such as XML allow for easier mixing and matching of applications, the applications themselves are written almost exclusively in C.

The ultimate goal of tools that raise design to a higher level of abstraction is to make it easier for engineers to design systems-on-a-chip (SoC), thereby getting more functional bang out of every chip. However, rather than making designers more productive, its likely to create new problems. Today, systems are assembled from individual components with well-defined interfaces that allow them to work together, even if they have different power management and timing closure requirements. Cramming all that functionality onto a single chip means that knotty problems such as power management and timing closure must be solved on the chip, creating new interdependencies where none existed before.

This is not to say that SoC doesn't have the potential to make designers more productive. "It's meaningless to compare SoC design costs with ASIC design costs," says Gary Smith, EDA analyst at Gartner Dataquest. "The comparison must be between SoC and designing a system out of discrete components." However, the SoC concept assumes that chip designers can easily make the transition to system design, even though they may have been trained for years to think in terms of circuits rather than systems. And piling more complexity onto designers' plates may not be prudent just when they're simultaneously struggling with a virulent infestation of RET-mandated design rules.

Crisis or opportunity?
That EDA's future is fraught with challenges is not necessarily bad news for EDA vendors. In fact, they need a continual supply of challenges in order to keep growing, according to Mentor Graphics CEO Wally Rhines. "The problem with EDA is that the problems have not become difficult fast enough to generate a lot of demand for existing methodologies," he explains. "We grow our business only when a new methodology comes along."



"What most people are doing today is 'electronic design assistance,' not 'electronic design automation.'"
—Rajeev Madhavan, CEO, Magma Design Automation

EDA vendors are hoping the combination of DFM with SoC will revive the flagging customer-owned tooling (COT) business model, in which EDA vendors could sell their design tools to a wide range of companies. Not surprisingly, because their future depends on this rosy scenario, there's a tendency among EDA execs to pooh-pooh the idea of an EDA crisis at 45 nm and beyond. "When we moved from 180 nm to 90 nm, there were a lot of problems with signal integrity and everyone was predicting the end of EDA," says Rhines. "But a bunch of startup companies sprang up to help us cope with the complexity. We've been here before."

However, EDA vendors prosper as the result of solving challenging problems, not simply as a result of identifying them. And it's here-in the area of automated solutions-that the EDA vendors seem to be falling short. One indication of a wide-ranging failure of EDA firms to provide sufficient tools to the semiconductor industry is the growing number of designers who use homegrown tools, a number that has tripled, from a low of 9 percent in 1997 to 27 percent in 2004, according to Smith. "People are complaining that the EDA guys aren't supplying the right tools on time," he says. In fact, the use of homegrown EDA tools is growing much faster, on a year-to-year basis, than commercial EDA use (see the chart, "Relative Industry Growth," above).

Growing dependence on homegrown tools-combined with an elaborate, collaborative design process to achieve DFM at 45 nm and beyond-means that SoC design will be increasingly expensive. Not only will design firms be forced to allocate precious engineering resources to building their own tools but they'll also be forced back to the drawing board as a result of ongoing and iterative negotiations with photomask and foundry experts. "Individual tools and solutions are not enough for dealing with and resolving this complexity," explains Boris Petrov, managing partner of The Petrov Group. "The scope of the problem requires more than one, two, or three individual companies' efforts."

The DFM-via-collaboration scenario represents a real danger for commercial EDA vendors. Higher design costs, combined with continuing difficulties in achieving an acceptable yield, may cause the market for EDA tools to implode, by changing the basic economics of chip design. If it simply costs too much to design new chips at 45 nm, semiconductor firms will build only custom chips for applications that require millions of chips and semiconductor firms with lower-volume applications will simply turn to FPGAs, structured ASICs, or other programmable technologies.

The combination of DFM and SoC, without significant advances in automation, may thus leave EDA vendors with a greatly reduced customer base. EDA vendors may continue to sell to a handful of vertically integrated SoC builders that have the high-volume applications that justify a customer's 45-nm design. However, just like IBM and Intel, those firms would tend to build their own EDA tools, further reducing the market for generalized EDA. At the same time, design firms that in the past would have purchased traditional EDA tools will increasingly use tools that target standard, cheap, programmable chips (presumably designed and manufactured by one of the vertically integrated giants).

"Individual tools and solutions are not enough for dealing with and resolving this complexity."
—Boris Petrov, The Petrov Group

If there's a crisis in EDA, it's because EDA vendors are exhibiting both too much imagination and too little. Trying to simultaneously automate both DFM and SoC may simply be too ambitious, even for an industry that, like EDA, has a long history of innovation. At the same time, assuming that the semiconductor industry will wait while the EDA segment plays catch-up is a serious failure of imagination. You see, it's all about productivity versus yield. If the EDA vendors can't deliver one or the other (or both), they can't expect the semiconductor industry to pay big bucks for new tools.

What do EDA vendors need to do to get over its upcoming obstacles? Send your thoughts to www.feedback@eb.mag.com

Geoffrey James writes EB's monthly EDA column as well as regular features for the magazine.