For voltage regulation modules (VRM) that power the latest generations of computer central processing units (CPU), power supply designers have historically used multiphase interleaved buck converters. These VRMs were designed to meet the tight Pentium 4 and Athalon CPU voltage regulation and transient requirements. The interleaved step-down converter is ideal for this low voltage, high current application due to its reduced input capacitor RMS current, reduced output capacitor ripple current, and smaller output capacitor bank as compared to a standard buck converter. Designers can gain the same benefits from interleaving two buck converters by interleaving two forward converters. In high current applications, such as intermediate bus or merchant power, using an interleaved forward converter may be more beneficial than a standard forward converter topology.
Traditional forward converterA forward converter has discontinuous input current that needs to be filtered through the input capacitor (Cin). This results in a high input capacitor RMS current (Icin).
Figure 1: Forward converter input and output capacitor current waveforms. The output filter inductor (L1) is sized with an inductor ripple current (∆IL1) based on roughly 25 to 30 percent of the output current (Iout) to meet output ripple voltage requirements (Vripple).
The output capacitor (Cout) is sized to suppress the inductor ripple current in order to meet output voltage ripple requirements. The following equations can be used to estimate the maximum equivalent series resistance (ESR) and the minimum output capacitance (Cout). In normal practice the ESR requirement dominates the capacitor's selection, resulting in more capacitance than needed to suppress the inductor ripple current.
Benefits of an interleaved dual forward converterAn interleaved forward converter is simply two forward converters operating 180 degrees out of phase, providing the benefit of reduced input capacitor RMS current and output capacitance ripple current.
Figure 2: Interleaved forward converter. Each forward converter has discontinuous input current (i.e. It1 and It2). The converter's input current is the sum of these two discontinuous input currents and, because they are 180 degrees out of phase, the input current becomes more continuous approaching DC. The input capacitor (Cin) only has to filter the AC portion of the input current and is drastically reduced by interleaving the two converters.
Figure 3 shows the RMS current reduction.
Figure 3: Interleaving reduces input capacitor RMS current (Icin) and reduces output capacitor ripple current (Icout). The output current (Iout) in this interleaved converter is the sum of the two inductor (I1 + I2) currents less the capacitor current (Icout). The output capacitor (Cout) in this application also has to suppress the AC portion of the output filter inductors. However, because the two converters are operating 180 degrees out of phase, the inductor ripple currents cancel each other, providing a more continuous output current. This reduces the amount of ripple current that Cout has to suppress. The output capacitance is sized similarly to the forward converter for output ripple voltage requirements. Except, the output capacitor does not have to suppress the entire inductor ripple current. This allows for a greater allowable ESR in the output capacitance.
Theoretically, this topology's output inductor ripple current cancellation property allows the designer to reduce the size of the filter inductor. However, the inductance generally needs to be the same size if not larger in order to reduce the total losses in high current applications [1].
Best capacitor ripple current reduction occurs at 50 percent duty cycle (D)It is important for the designer to know that the maximum reduction in capacitor current occurs at 50 percent duty cycle.
Figure 4 shows the input and output capacitor current wave forms at roughly 40 percent duty cycle. Because the duty cycle is less than 50 percent, the input current to the interleaved converter is less continuous and increases the input capacitance's RMS current. The output inductor ripple currents are no longer symmetrical and do not cancel when the converters are operating at 50 percent duty cycle. This increases the amount of capacitor output ripple current.
Figure 4: Ripple current reduction is decreased as the duty cycle (D) varies from 50 percent. The following equations and the graph in
Figure 5 show how the capacitor RMS current (Icin(RMS)) behaves with changes in duty cycle, where N is the transformer turns ratio. It can be observed that the lowest input capacitance RMS current occurs at 50 percent duty cycle and the highest RMS current occurs at 25 and 75 percent duty cycle.
-Input capacitance RMS current at D < or = 0.5
-Input capacitance RMS current at D > 0.5
Figure 5: Input capacitor RMS current. The following equations and graph show how the ratio of output capacitor ripple current (∆Icout) and the change in inductor current (∆IL) change with duty cycle.
Figure 6 illustrates that the maximum inductor ripple current cancellation occurs at 50 percent duty cycle.
Figure 6: Graph of ∆Icout/∆IL vs duty cycle. Design considerationsDesigning an interleaved forward to get the maximum reduction in filter capacitor currents requires the proper selection in duty cycle range. This can be achieved by adjusting the transformer turns ratio (N) per the design's input and output voltage requirements.
The following equation can be used to estimate N where Vin(min) is the minimum input voltage and Dmax is the chosen maximum duty cycle. Vd represents the forward voltage drop of the output diode.
Once the maximum duty cycle and transformer turns ratio have been determined, the minimum duty cycle (Dmin) can be calculated. With this information and the graphs in
Figures 5 and
6, the design's worst case filtering capacitance currents can be determined.
Design exampleA dual interleaved forward converter was constructed using the UCC28221 interleaved PWM controller to show how much the capacitor ripple current could vary with duty cycle. The 200W converter was designed for input voltage range of 36 to 76V with a regulated 12V DC output. The two-to-one variation in input voltage would result in roughly a two-to-one variation in duty cycle. To optimize transformer reset and reduce capacitor current, a maximum duty cycle of 0.6 was chosen for this design. Each converter was designed for 500kHz switching frequency (fs) in order to keep the size of the magnetics down. The output diodes for this design were Schottky diodes and had Vd of roughly 0.3V. This resulted in an N of 1.75-to-1 and a minimum duty cycle of 0.28.
To keep the peak input currents to the forward converter down, the output inductors were designed for a 60 percent ripple current. This would result in a filter inductor of roughly 3.5uH. This is approximately the same size inductance used in a single switch forward sized for an inductor ripple current of roughly 30 percent of the maximum load current (Iout).
The output capacitance ripple specification for this design was 200mV (Vripple) max. The output capacitor ripple current is at its greatest when the power converter is operating at 0.28, the minimum duty cycle. The output capacitance needs to suppress this ripple current to meet output ripple requirements. The graph in
Figure 6 shows that the output capacitance's ripple current is roughly 60 percent of the filter inductor's ripple current. This would result in a capacitor ripple current of roughly 3A (∆Icout). This design requires an ESR of less than 66mΩ to meet output voltage requirements.
The maximum allowable ESR for a forward converter design in an identical switching frequency and power level would be roughly 40mΩ. The interleaved converter allows the designer to use 1.7 times more maximum allowable ESR, as compared to the standard topology in this design. These results will vary depending on design requirements. If the converter was designed with a minimum duty cycle of 0.4, the maximum allowable ESR for a design at the same power level and output ripple requirements would be 120mΩ. This is roughly three times the allowable ESR of a standard forward converter.
The output capacitor RMS current (Icout(RMS)) for this design would be roughly 1.74A, roughly 60 percent of what it would have been for a standard forward converter.
The input capacitor RMS current would be the highest at roughly 28 percent duty cycle (D) for this design. The highest input capacitor RMS current would be roughly 2.4A. A traditional forward converter designed with similar power levels would have an input capacitor RMS current of roughly 4.7A. Using an interleaved converter would reduce the input capacitor RMS current by roughly 50 percent in this design.
The following oscilloscope waveforms show how the ripple current cancellation varies with duty cycle.
Figure 7 was taken when the power converter was operating at 50 percent duty cycle. The sum of the two output inductor currents (IL1+IL2) is almost DC, resulting in almost no output capacitor ripple current.
Figure 7: Current ripple cancellation at 50 percent duty cycle.
The oscilloscope waveform in
Figure 8 was taken with the converter operating at a maximum line voltage of roughly 76V. Regulating the 12V output correctly requires a duty cycle of roughly 28 percent. From the oscilloscope waveform it can be observed that the sum of the inductor currents has a 3A peak-to-peak ripple current that would need to be filtered by the output capacitor. This peak-to-peak capacitor ripple current (∆Icout) was roughly 60 percent of the inductor ripple current.
Figure 8: Current ripple cancellation at 30 percent duty cycle. ConclusionThe dual interleaved forward converter may be beneficial for high current/ high power density designs. This converter topology would be ideal for intermediate bus converters and merchant power applications because the reduced input and output capacitor ripple current reduces electrical stress on the input and output capacitors. The inductor ripple current cancellation of interleaving converters allows the design more output capacitance ESR, which in turn should reduce the design's output capacitance requirements.
Author InformationMichael O'Loughlin is a high performance analog (HPA) products customer applications engineer for Texas Instruments. He has worked at Texas Instruments/Unitrode for more than 11 years. Michael graduated with a BSEE from the University of Massachusetts.
ReferencesSophie Chen, Using the TPS40090EVM-001, User's Guide, Texas Instruments Literature Number SLUU175, p9
Brian Shafer, Interleaving Contributes Unique Benefits to Forward Converters and Flyback Converters, Texas Instruments Power Supply Design Seminar, Topic 4, SEM 1600.
