Taiwan Semiconductor Manufacturing Company (TSMC) has introduced Reference Flow 7.0 that features a powerful statistical static timing analyzer (SSTA), a set of new power management techniques and an array of design for manufacturing (DFM) enhancements. It also adds a Magma Design Automation design implementation track to the existing Cadence and Synopsys design tracks for easy adoption of TSMC's 65nm process technology.
"Extensive collaboration with our EDA design ecosystem partners has become the hallmark of TSMC's Reference Flows and this year is no exception," said Ed Wan, senior director of design services product marketing. "Reference Flow 7.0 continues to lower design barriers for 65nm designs and provides a proven path to success."
TSMC first opened the door for designers targeting 65nm process technology in 2005 with Reference Flow 6.0. Since then, new tools and services have been integrated into the flow and validated on TSMC's industry leading 65nm technology.
"Synopsys and TSMC have been collaborating to address the challenges of 65nm IC design," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "One of the emerging requirements is to manage the uncertainty introduced by process variation. Our statistical timing analysis and extraction solutions are a very significant extension of our widely deployed sign-off tools, helping ensure accuracy and predictable silicon performance. Together with many new technologies throughout our Galaxy(TM) Design Platform, including IC Compiler, we are delivering a comprehensive RTL-to-GDSII solution in the TSMC Reference Flow 7.0 today."
"The integration of Quartz SSTA's statistical timing analysis capabilities in TSMC's Reference Flow 7.0 Magma IC implementation track is a technological breakthrough that will enable designers to address process variations in nanometer designs," said Kam Kittrell, general manager of Magma's Design Implementation Business Unit. "We're very pleased that our software is incorporated into the TSMC Reference Flow 7.0, which reinforces our commitment to working with TSMC to speed ramp up on 65nm and lower process technology."
"To keep the design intent, it is critical to verify and validate design functionality during various power-off states to achieve low dynamic power," said Jim Miller Jr., executive vice president, Products and Technologies Organization at Cadence. "TSMC and Cadence have collaborated to meet the low-power design challenge in the new reference flow. Integrating low-power design methodology and power-management library improves designers' productivity and achieves project targets with reduced cycle time."
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