Cadence Design Systems, Inc. has announced that Fujitsu Limited has adopted Cadence Encounter Timing System (ETS) for timing analysis in their implementation flow. ETS delivers superior signoff timing accuracy, usability and functionality for designs at 90 nanometers and below.
The Encounter Timing System provides full-featured integrated static timing analysis (STA) and signal-integrity (SI) analysis delivering consistency through physical implementation, optimization and timing signoff. ETS builds upon Cadence's industry-leading SI signoff solution, Encounter CeltIC Nanometer Delay Calculator (NDC), and extends to include signoff STA delay calculation, and the popular Encounter-based global timing debug features for quick and easy identification and optimization of timing issues and exceptions.
"After evaluating and testing ETS on multiple production designs, it is clear that ETS will deliver benefit in terms of signoff accuracy, feature set, and productivity," said Satoshi Andou, general manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu Limited. "ETS met our timing signoff requirements and we are now incorporating ETS in our ASIC implementation flow. We are also looking forward to extending the collaboration with Cadence toward statistical STA to remove the pessimism in timing imposed from process variation."
"Cadence and Fujitsu have collaborated for several months to meet timing signoff requirements. We are very pleased that Fujitsu, one of world's leading ASIC suppliers has chosen to adopt and support the Encounter Timing System for timing signoff," said Wei-Jin Dai, corporate vice president of R&D at Cadence. "With ETS, we now offer Fujitsu a complete system-on-chip platform from netlist to GDSII."
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