Raj Master, a Senior AMD Fellow, spoke to EDN Asia on the problems and prospects of semiconductor packaging. He was responsible for successfully transferring IBM micro-processor packaging technologies to AMD, and for setting up high volume manufacturing in Penang. EDN Asia: As we go more into deep submicron, what challenges does packaging design face?Master: While lithography is advancing, packaging technology has been unable to keep pace. Few years ago, making silicon was an over-whelmingly important job in the entire process of chip making. On a percentage scale of importance, silicon making commanded 90 percent importance, while packaging and testing, merely 10 percent. Today, silicon making has 60 percent importance; while packaging and testing, 40 percent. In five years, both will have the same importance. With increase in the functionalities of silicon, the design of silicon has become very complex, which is driving the packaging industry. For instance, in a die there are many layers. Interphase is getting stressed because of different expansion due to heat. With increase in the number of connections, again the design of packaging becomes complex.
In 1996, there used to be about 700 connections between chip and die. For 130 micron designs, the number of connections has risen to 4,000. At 90 and 65nm, the number of connections will go up to 10,000. Will these numbers of connections drive technology to its limit? If you have the silicon, but don't have the required number of connections, then what do you do?
No satisfactory solution seems to be emerging. While semi-conductor makers are bogged down with this problem, there is another problem that is even more difficult. If you build up the package, how will you cool it? If the package does not cool, both semiconductor and packaging will burn. Designers have realized that an integrated solution is required to address the problems. Earlier, you had silicon guys working only on the silicon; packaging guys working only on packaging. But now they are working together to find an integrated solution.
EDN Asia: Is there any integrated effort by companies to pool their talents and resources to tackle the common problems?Master: Yes, companies are coming together to form consortiums that are working on various aspects of the problems. Institute of Materials Research Engineering (IMRE) and Electronics Packaging Research Consortium (EPRC) are among such consortiums.
EDN Asia: Any progress in the activities of the consortiums?Master: Unlike in the last few years, there will not be any incremental improvement in the situation. What is needed now is thinking outside of bars. Solutions may emerge, but the challenge is to make the solutions cost-effective. The collaboration is now going even beyond consortiums. Academics, suppliers and users are also getting involved in addressing the problems.
EDN Asia: In view of the pervasive feeling that collaborations are a must to solve the problems, are there any chances of leading companies like Intel and AMD coming closer to collectively tackle the problems?Master: At the company level, the two companies are unlikely to collaborate in the foreseeable future. In the consortiums, all companies work together.
EDN Asia: Which areas are at the limit of current state-of-the-art?Master: Among such areas are Flip Chip Bumping, organic and ceramic package manufacturing, and ability to cool packages. Full low-K stack in the die is a special situation where these problems are aggravated even further. What makes problems even more complicated is that many of the needs are conflicting in nature. For instance, the package and die bump pitch needs to decrease with shrinking lithography rules from 130 to 65nm, but that conflicts with their ability to carry high current. If we are able to carry high current, then we are unable to provide the thermal cooling solution required for such high power.
You can reach Kirtimaya Varma at
kirti.varma@rbi-asia.com
