EDA's Ebb and Flow

Aart de Geus, Chairman and CEO of Synopsys, sat down with Electronic News/Electronic Business to talk about growing complexity, the shrinking number of EDA startups and why customer-developed tools are on the wane. What follows are excerpts of that conversation.

Q: One of the biggest costs in designing a chip is verification. Will that ever change?
De Geus: It's absolutely the biggest cost, and it will keep growing as a cost. The verification problem is growing more rapidly than the complexity of Moore's Law. That is because the state space is expanding so rapidly compared with the number of transistors you have. There are ways to restrict that by having more disciplined design methodologies, but in general verification is growing like a weed. The good news is they have made a number of very big steps in the last few years to help rein it in. One is that the space of raw simulation has been combined in better and better fashion with what it takes to do test benches, to do assertions, to do coverage metrics. And it has been integrated fabulously well, and therefore you can run it much faster. Second, it's being set up so you can run it on large compute farms. We see some of our customers with 10,000 or more computers devoted to verification. If we fast forward, we can see multicore will make that more possible.

Q: Can that ever be broken down into distinct segments that can be parsed out to take advantage of multicore processors the same way databases do?
De Geus: Absolutely. People have an enormous set of test cases. There is no reason you have to run those one after another. You can very often split it up. The question is can you also split up the actual test design, and in some cases that's possible, as well. We're going to see a lot of evolution in the coming years on that. We started with the premise of whether that's big problem in the first place, and the answer is yes. About 3-1/2 years ago we introduced System Verilog as a promising language. There were a lot of skeptics at that time: "Why do you need another language, why is it better?" Today there is no doubt it is much more powerful with the integration of assertions, for example. Second, it is much more efficient. Evidence is clear you get a 3:1 reduction in the amount of code to represent the same functionality. That's huge because the number of lines of code is directly related to the human error level, and that doesn't change that much. Right there is a very big change in efficiency. And third, the question is, "Do the dogs eat the dog food?" And the answer is yes. If you look at the growth rate of System Verilog, it is moving very, very quickly because the productivity is much higher.

Q: So what you've done is break everything down into modules that can be repeated concurrently, right?
De Geus: That's one of the things that people can use to take advantage of a whole new generation of how computers are going to look. The funny thing here is that we are the very ones who mastered Moore's Law, and use it to master Moore's Law. It's like, "Please have faster computers so we can have faster computers." It's a self-supporting cycle.

Q: That's like dogs making dog food. But as a result of that, what will happen to the time it takes to develop chips and the cost of those chips?
De Geus: As much as there is desire to reduce the time, there's a natural economic cycle that says, "If you can do it faster, why not add more functionality?" The development is just one portion of the cycle. The introduction of a product, the rollout—they all have a large amount of cost and effort to them. If you develop a camera, and if you could develop the next version of that camera the next day, you'd never make any money. You need a certain amount of time for something to be rolled out to the market and to get a return. If you go too fast, you don't get there.

Q: How about derivative chips?
De Geus: They can go faster, but from an economic point of view it's still the same question about when you want to be on the market. But for derivative chips, you can make modifications so you can tune it to a given market segment. That is how people increasingly make money—build a platform that is suited for derivatives.

Q: That changes the idea behind an ASIC or ASSP, though, doesn't it? It's like building the core of a chip and then modifying what's around it.
De Geus: That's absolutely right. But it's even broader. It's not just the core of the chip. It's a platform. With the chip comes a lot of embedded software and application software. You want to make sure you fully encompass that in the thinking when considering derivatives because the software will have derivatives, as well.

Q: By that thinking, the cost doesn't necessarily go down for developing a single chip, but it does go down for a series of chips. Is that right?
De Geus: Yes. Simultaneously, the lifecycle and the volume keep growing around a platform. There will be fewer platforms, they will be much more complex, and you will try to do many more derivatives from them.

Q: Is this the future, or is this is something you're starting to work on now?
De Geus: It's already here today. If you look at sophisticated designs of, say, a mobile solution, a DSP solution, a graphics solution, these are all platforms designed in that fashion. There is a major platform and a large set of derivatives. How well will Moore's Law continue is a separate question that supports that vision. We have strong evidence there are a number of generations in the works that are being used. We track the number of 65nm and 45nm designs, and 65nm is growing at exactly the same ramp as 90nm delayed by two years exactly and 45nm is growing at exactly the same ramp as 65nm delayed by two year; 32nm is still full of question marks, and 22nm is in the very early stages. After that, it's all speculation that falls into two categories. One is doom and gloom, as it has been for the last 20 years. It's a question of the economics and volume. What is clear is we do see the increase of chips with very high volume. Those are the ones driving the advanced utilization of silicon.

Q: Will chips become more general as the cost rises so that more companies can utilize the design?
De Geus: We're going to go more and more toward a block-based assembly process. The building blocks that are available are of a sophistication that is amazing, if you were looking at this 10 years ago. The entire process of subsystems—communications, graphics, encryption—these are all building blocks that are available commercially today. A lot of the skill set involves how you assemble something with value from that. Do you link it to the embedded software, and how do you do that without falling to the yield trap, because yield has a very direct economic impact on the success of these chips?

Q: This sounds like the current argument between IBM and Intel over air gap technology.
De Geus: Intel and IBM are driving the state of the art forward. We saw the same arguments about copper and low-k dielectrics. The reality is all of these techniques get proven out over time, but they have to be pioneered by someone who can make the investments and who has the courage to do it. Kudos to those companies.

Q: You mentioned low power. That seems to have a new market at the computer server level now, as well. Is that a new opportunity?
De Geus: We have been massively involved in this for awhile. If you look at the compute farms, the cost of infrastructure and heat dissipation is now about as big as the capital cost of the equipment in the first place. A number of large semiconductor and computer guys have teamed up to see if they can go more "green" in the future. From the external world, there's a green emphasis, anyway. But in the short term, the cost of compute farms is too high.

Q: How does green translate into the EDA world?
De Geus: In our world, we already see some of that with TCAD—technology computer-aided design. That applies to process development and device development. There are many different devices, from power-control devices all the way to solar cells. Being able to do three-dimensional dynamic simulation of how these things work is a pretty exciting set of techniques is pretty exciting.

Q: To a large extent, the big EDA players have been built with the acquisition of startups. Is money starting to filter into the EDA startup market again, or is there simply no exit strategy to make that work?
De Geus: The money that is going into EDA startups is dramatically down. For many years, the strategy was to be acquired because the large guys were trying to get to a complete solution and they were afraid the others would get there first and they would be stuck. Today I think we're managing our companies much better now for a healthier financial profile. If you spend all your money acquiring high-priced startups, that may be important technically but you're not going to grow your business profile. We have become much more careful in terms of what we do there.

Q: So what becomes of the new technology that was created by startup innovations?
De Geus: In any field that grows older, the nature of innovation starts to change. Much of the innovation is systemic. In cars, it was important to develop the latest and greatest carburetor or transmission, but if you are concerned about gas mileage you have to look at how all these things work together. We see this in chip design. You may have a startup that comes up with a better solution for testing, but it's not going to work unless you take those ideas and integrate them systemically so you can solve all the problems at the same time.

Q: But in the past you were able to take pieces out of the market in the form of startup technologies and apply them into your platform. Is that still possible?
De Geus: In the past, that was equally true for our customers. They would glue together their own flows out of best-in-class pieces. That worked, and then it worked less, and then it stopped working altogether. Suddenly you have these Frankenstein flows where one tool does something brilliant that the next tool downstream has to brilliantly reverse. On the positive side of that, we released a new version of our synthesizer design compiler. It is clairvoyant. It knows what is going to happen downstream in the place and route so it doesn't make stupid decisions that will lock up the place and route. That clairvoyant knowledge has huge impact on the number of iterations you have to go instead of gluing together tools that do not know about each other. This is like doing a very fast place and route without doing it. There's always a tradeoffs can you make with a minimum amount of effort.

Q: So basically you're assessing all the possible permutations and taking the most logical ones?
De Geus: That's the intent.

Q: Because of all this complexity, is your R&D budget changing from the 30 percent number you talked about last year?
De Geus: No. It's still huge, but if we could have another 30 percent it would be eaten up tomorrow. The opportunity space is so high for us now that we have a platform to get the power down, get better yield. We have an incredible wealth of technology at Synopsys. It stretches from high-level systems down to virtually a few atomic layers. It is literally seven to eight atoms.

Q: In low power, is there anything new on the horizon?
De Geus: For those who work with this, it's not new. But the ability to dynamically change the voltage is a function of the throughput of the calculations. Together with ARM, Synopsys has built an infrastructure to raise and lower the voltage as a function of the throughput of instructions. You can monitor this. You can watch an image being processed, and the processor goes really hard with blue sky in the background, and then it's all blue sky. It changes quickly. You can see that different tasks require different levels of energy, so why have them all on all the time?

Q: Does that become easier or harder with multiple cores?
De Geus: "More difficult" has been the bane of our existence for 40 years. We've been wide awake. This is what makes our job so fascinating. Tomorrow is harder than yesterday, and yesterday looks trivial compared to today.

Q: So what is the major challenge for Synopsys?
De Geus: We are bringing all these pieces together. More and more of our customers have to bring them together, as well. They have to move toward more disciplined design flows that are integrated, and over time abandon these glued-together flows. Their design methodologies are clearly evolving to a higher level of abstraction. This is the nature of EDA. We used to work with rectangles, that became gates, that became small macros, that became building blocks, that became large blocks, that became hardware/software blocks, that became entire subsystems. That's proving to higher level of abstractions in order to manage complexity.

Q: But as you move to higher levels of abstraction, you also see less of the detail below.
De Geus: You trust more and more of it is actually working due to automation and proven verification. Today we are unhappy when we are driving at 60mph through a tunnel and an e-mail is not downloading instantaneously onto a Blackberry.

Q: Do you lose some of the capability to innovate at the low level by doing that?
De Geus: No, I see the opposite. Because you have this stable point in the middle in the core design flow, there are extensions in both directions. There are extensions out to smaller geometries, and please hide it from the guy doing high-level design. All things that are yield-oriented and feature-oriented we need to automate. At the same time, we see the same level of expansion to the higher level. Now that we have 45nm transistors, that's a lot of potential functionality on a chip.

Q: Isn't that almost too much?
De Geus: This goes back to the IBM executive who said there will only be a need for five computers in the world. We have a pretty good view of the two- to three-year horizon for applications. The 10- to 20-year horizon turns out to be surprising. The Internet has been the most surprising thing. I would predict now that high-definition video will be everywhere.

Q: There are fewer companies developing chips independently because of the cost, and much of the work is now being done with consortiums. Does that help or hurt EDA?
De Geus: The amount of design work is about the same. What we are seeing is there are groupings of people developing technology. The IBM Common Platform is one of those. TSMC has a center of gravity. There are large guys like Intel. But the cost of developing the next generation is so high that people are teaming up.

Q: Does having a broad-based platform provide internal synergies for development?
De Geus: Absolutely, and I cannot emphasize that enough because it was so difficult to get there. After we bought Avant!, which brought a whole set of physical design tools to the company, the difficulty of bringing that together into a coherent platform was huge. It took us two or three years to do it, but once it was there, suddenly the progress was enormous. And that was just on the implementation platform. On the verification platform we have done the same and brought together the simulation, the formal verification and the assertion management and the test bench capabilities. It's all in one platform and highly integrated.