Sonics Inc., a supplier of system-on-chip (SoC) SMART Interconnect-solutions, has released the MemMax RD, a new version of its MemMax Memory scheduler solution that contains a seamless interface and pre-verified configuration and initialization settings optimized for the Synopsys DesignWare DDR2 SDRAM Protocol Controller intellectual property (IP). Connecting MemMax RD to the DesignWare DDR2 SDRAM Protocol Controller IP "out of the box" has demonstrated greater than 5GBps external memory bandwidth and over 80 percent channel utilization, while satisfying the throughput and quality of service (QoS) requirements for demanding applications such as high definition video streaming.
The availability of MemMax RD comes as a result of the two companies successfully collaborating on a system on chip (SoC) SDRAM memory subsystem reference design, which outperformed a production subsystem based on a proprietary DDR2 controller design for high-definition television video streaming. SoC developers can now utilize the MemMax RD and the Synopsys DesignWare DDR2 SDRAM Protocol Controller and PHY IP components for multicore SoCs and achieve ultra-high memory bandwidth with significantly reduced engineering effort.
The emergence of multicore SoCs as a defacto standard architecture in the convergence era has dramatically complicated SoC data flow management. Among the many data flow services required, advanced arbitration schemes either inside the SoC interconnect or designed as part of the memory scheduling logic must provide QoS to satisfy the performance requirements of each processor’s access to a shared external memory channel, while still achieving very-high channel utilization. The channel utilization, defined as the fraction of SDRAM clock cycles in which useful data is sent or received, determines the type, frequency, and configuration of external DRAM components that are required to achieve a given level of system performance.
Multicore SoCs require complex memory scheduling algorithms to be built into the memory subsystem to achieve the required channel utilization and QoS. Such memory schedulers choose requests from the different processors to exploit the bank-level parallelism of the memories and optimize in-page operations to maximize throughput, and independent scheduler ports per processor are traditionally required. The breakthrough represented with MemMax RD is its ability to use only a single multi-threaded interface featuring non-blocking flow control to enable the interconnect to multiplex the processor traffic while delivering both high channel utilization and excellent QoS. MemMax RD offers significantly lower average and worst-case latency to high-priority processor traffic and higher channel utilization than other approaches that share a single out-of-order port between the interconnect and memory controller.
MemMax RD seamlessly connects to any Sonics SMART Interconnect solution. This allows SoC developers to rely on Sonics' proven multi-threaded, non-blocking flow control data flow management schemes from the processor through the memory scheduler.
The DesignWare DDR2 SDRAM Protocol Controller and PHY are essential components of the reference design high-performance subsystem. The combined solution provides designers with a seamless path from the MemMax RD scheduler to the DDR2 SDRAM protocol controller, utilizing the maximum available DDR2 memory bandwidth. The silicon-proven DesignWare DDR2 Memory Interface IP solution is optimized for improved data bandwidth, low power and enhanced signaling features, delivering predictable memory system performance of up to 800Mbps per bit lane and beyond.
SonicsClick here for more information on the DesignWare DDR2 Memory Interface IP solution
