Cadence Design Systems Inc. and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform. This new methodology uses Cadence SoC Encounter RTL-to-GSDII system for design and physical implementation and Cadence Encounter Timing System for design closure and final timing, signal integrity and signoff—both are key technologies of the CPF-enabled Encounter platform.
Using the combination of Denali's Databahn DDR controller and PHY IP with the Encounter technologies, customers can now achieve DDR memory-system implementations at 65nm and at speeds exceeding 400MHz.
This methodology combines innovative design techniques, and world-class implementation and analysis solutions enabling robust customer design kits, or complete IP hardening leading to the market's smallest and highest performance configurable DDR-PHY products. An estimated 70 percent of new SoC designs use DDR-memory-subsystem IP. DDR memory systems with superior system-performance requirements have become a critical factor for products in the networking, computing, and consumer-electronics segments where memory bandwidth is a critical factor for achieving system performance.
Additionally, due to dramatic increase in clock speeds and the storied challenges of 65nm implementation, the ability to implement DDR-PHYs and quick closure on timing has become a serious bottleneck to time to market. Some of the world's largest IDMs have declared this as their number one problem. After careful evaluation, Denali has standardized on SoC Encounter and Encounter Timing System for superior DDR-PHY design, physical implementation, timing closure, and signoff analysis. With this solution, Denali now delivers proven design kits, methodology services, and hardened IP to their customers.
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