ClariPhy Communications and Helic S.A. has announced details of their joint engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy's single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy's transceiver features a low-power 10G Analog to Digital Converter (ADC) and a Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.
ClariPhy selected Helic's EDA tool, VeloceRF, after diligent evaluation. The main requirement was synthesis and modeling of spiral inductors, but ClariPhy's designers found the Helic tool also valuable as an inductive parasitics (RLCK) extractor. VeloceRF was used to synthesize and model all the inductive content of the chip, including on-chip inductors and several critical, high-speed interconnects. VeloceRF enabled ClariPhy's designers to optimize circuit performance while minimizing silicon real estate. With inductance accurately calculated by VeloceRF, it was possible to mitigate detrimental effects before tapeout, and achieve excellent performance in first-pass silicon.
ClariPhy recently demonstrated its 10GBASE-LRM integrated circuit (IC) with industry-leading performance at OFC 2007. In response to the demand for a better performing product, ClariPhy has developed an all-digital CMOS solution integrating a low power 10G ADC and MLSD engine. The all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit.
"We knew from the start of this project that success depended on executing beyond the state of the art in mixed signal IC design," said Dr. Paul Voois, ClariPhy's CEO. "The engineering collaboration with Helic was instrumental in our first-pass design success. ClariPhy has pioneered the migration to an all-digital 10-Gbit/s PHY, and Helic's tool allowed us to implement our advanced product architecture with confidence."
"We greatly enjoyed working with the ClariPhy team and supporting them in this breakthrough design. It was exciting to see VeloceRF being used in a non-wireless application and deliver on the promise for first-pass silicon," said Sotiris Bantas, vice president of technology at Helic. "ClariPhy came to us with a demanding set of requirements, which was understandable considering their very ambitious product architecture. They leveraged the tool's capabilities and latest features, including spiral component synthesis in CMOS and inductance/mutual inductance extraction for accurate 10GHz simulations. ClariPhy is already a marquee customer for us, demonstrating VeloceRF as a winning methodology for high-speed and RF nanoscale CMOS design."
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