Xilinx, Inc., the world's leading supplier of programmable solutions, has announced that its Virtex-5 FPGA devices are interoperable with 800 Mbps DDR3 SDRAM devices from leading memory suppliers. Hardware-proven interoperability with Virtex-5 devices provides customers with an early path to adopt DDR3 SDRAM technology with the industry's only high-performance 65-nm FPGA family shipping in production.
Successful interoperability hardware tests were performed using devices from leading memory manufacturers, Micron Technology, Inc. and Elpida Memory, Inc.. Xilinx gives designers the ability to begin their designs today by offering DDR3 SDRAM support in its Virtex-5 LXT ML561 FPGA Advanced Memory Interfaces Tool Kit, which is shipping today.
"We are pleased to achieve interoperability with our DDR3 SDRAM devices and Xilinx's memory controller with Virtex-5 production silicon at 800 Mbps," said Raymond Fontayne, segment marketing manager at Micron Technology, Inc. "Solutions developed through industry collaboration, JEDEC standards compliance and interoperability testing provides an ecosystem where our customers can quickly develop platforms in multiple market segments. High performance memory sub-systems and FPGAs play a major role in a variety of applications including networking, automotive and security."
"Elpida and Xilinx have strategically partnered to enable new DRAM technologies in markets requiring high performance and cost effective solutions," said Bijan Yazdani, vice president of sales at Elpida Memory, Inc. "Through successful DDR3 and Virtex-5 FPGA interoperability testing, Xilinx will provide their customers with the first hardware verified FPGA controller for faster proliferation of DDR3 DRAM technology."
The DDR3 SDRAM architecture, as an evolutionary step from DDR2 SDRAM, provides increased bandwidth, lower power consumption (1.5 V vs. 1.8 V power supply for DDR2 SDRAM), and improved IO signaling for better signal integrity to enable higher system performance.
The interoperability tests performed on the Virtex-5 LXT ML561 FPGA Advanced Memory Interfaces Tool Kit verified a DDR3 SDRAM controller and interface reference design that is scheduled to be made broadly available in September. The reference design leverages Virtex-5 FPGA features like the IODELAY, a programmable input and output delay block that ensures accuracy of read data capture and configurable write data signals to achieve 800 Mbps data rates and DDR3 SDRAM functional requirements.
"Hardware proven reference designs are essential for early adopters of new architectures like DDR3 SDRAM, as we need to be in our competitive industry," said Sunny Chang, president & chief operating officer at KINGTIGER Technology (Canada) Inc. "Xilinx has worked with us so that we can successfully and quickly move up the learning curve of this new technology."
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