It is tempting to use an op amp to directly drive the input of a SAR (successive-approximation-register) ADC. Unfortunately, this configuration can limit circuit performance. An external RC (resistor-capacitor) network better isolates the converter from the driver amplifier and allows greater flexibility in op-amp selection. Getting the best performance from a SAR ADC may be more important than you think. Even if you convert signals that are well below the frequency limitations of the converter and amplifier, you can’t ignore the dynamic characteristics of the SAR ADC’s input structure.
Figure 1 shows a single-supply combination SAR-ADC/op-amp circuit. This circuit places the op amp in an inverting-gain configuration. IC1 is a unity-gain-stable, single-supply CMOS op amp with a gain-bandwidth product of 5 MHz. The single-supply configuration avoids the effect of the amplifier-input limitations, such as a limited input range and input common-mode-crossover distortion. The designer of this circuit uses the ADC-reference output to bias the amplifier’s noninverting input as well as the negative input of the ADC, thus keeping the op-amp operation between the supply rails. IC2 is a 12-bit, 500k-sample/sec SAR ADC.
In Figure 1, the circuit appears to be functional; the op amp’s low-impedance output drives the SAR ADC. Figure 2 shows the FFT-test results for this circuit, with a 15-kHz op-amp-input signal. In Figure 2a, the SAR ADC’s acquisition time equals 265 nsec. In Figure 2b, the acquisition time is 560 nsec. These acquisition times extend neither the op amp nor the ADC beyond its specified performance limits.
The measurement results show that the length of the acquisition time affects the performance; increasing the acquisition time from 250 to 560 nsec improves the performance, although increasing the acquisition time also slightly increases the total throughput time. With the longer acquisition time, the SNR (signal-to-noise ratio) increases from 70.8 to 71.5 dB and the THD (total harmonic distortion) decreases from –71.4 to –78.6 dB (Reference 1).
Standard SAR-ADC model
A capacitive SAR ADC’s input stage contains a capacitive-charge-redistribution network (Figure 3 and reference 2 and reference 3). In Figure 3, VSH0 is the initial voltage across the sampling capacitor, CSH. Depending on the converter’s input structure, this voltage can equal the input during the previous conversion, ground, or VREF. Opening S2 and closing S1 cause signal acquisition. When S1 closes, the voltage across the sampling capacitor, CSH, changes to VIN. Charge from the voltage source, VIN, passes through the sampling-switch path of S1 and RS1 onto CSH. As the charge redistributes itself, the charge previously on CSH changes so that VCSH equals VIN (Figure 4).
If you consider only the ADC input, the ADC’s bandwidth depends on the internal sampling capacitor, CSH, and the switch resistance, RS1. From the time constant, τ=RS1×CSH, you can derive the settling time of this one-pole system. The minimum acquisition time for the SAR converter is the time required for the sampling mechanism to capture the input voltage. The acquisition time begins after the issuance of the sample command and the charging of the hold capacitor, CSH.
You can use the following equations to determine the settling time for the network in Figure 3.
(1)
where VCSH(t) is voltage versus time across the sampling capacitor, CSH; VCSH(t0) is voltage across the sampling capacitor, CSH, at the start of the acquisition time; VIN is the ADC’s input voltage; τ is the acquisition-time constant, equal to RS1×CSH; and t is a time variable in seconds.
If you want the error not to exceed ½ LSB, the time at which the voltage on the sampling capacitor, CSH, approaches within ½ LSB of the input voltage establishes the acquisition time.
(2)
Or
(3)
where VCSH(tAQ) is voltage across the sampling capacitor, CSH, at the end of the sampling period, and tAQ is the acquisition time, or the amount of time from the beginning of the sampling period (t0) to the end of the sampling period. Further,
(4)
where FSR is the input full-scale range of the N-bit converter.
If you change VCSH(t) to VCSH(tAQ) and VCSH(t0) to VSH0 and make equation 1 and equation 3 equal, you can derive the following equations:
(5)
Or
(6)
If
(7)
then
tAQ≥k×t. (8)
You can calculate settling time as a function of the input-stage time constant and the time-constant multiplier, k, for a variety of ADC resolutions. Table 1 summarizes these calculations. You can use these calculations to evaluate the acquisition time of any SAR ADC. For the worst-case analysis (Equation 5 and Table 1), assume that VSH0 equals 0V. Figure 5 shows the change of the initial charge of the Texas Instruments ADS8361, a 16-bit, 500k-sample/sec SAR ADC, as a function of the input-signal amplitude.
With the ADS8361, S1’s closed-switch resistance, RS1, is 20Ω. The ADS8361’s internal sampling capacitor, CSH, is equal to 25 pF. From Figure 5, you can see that the sinusoidal input voltage frequency is much lower than the converter’s sampling frequency. If you measure lower input frequency signals, fIN≤fS/10, the calculation uses an initial voltage on VSH0 equal to half of the full-scale range. On the other hand, if there is a front-end multiplexer, VSH0 is 0V. For a 16-bit SAR ADC, the time-constant multiplier, k1, for 1-LSB error equals 11.09. If you need ½-LSB error, k2=11.78. The detailed discussion in Reference 4 explains how to determine the initial charge of the sampling capacitor in a capacitive SAR ADC.
A charge bank at the SAR-ADC input
Figure 6 illustrates a driving amplifier, followed by an RC pair that connects to the input of a SAR ADC. The capacitor, CIN, acts as a charge bank that supplies ample charge to the SAR ADC’s internal capacitor array. Using the previous calculation for a 16-bit SAR ADC, the time constant, τ (τ=RIN×CIN), of the external RC filter in which k2=tAQ/τ is between 11 and 12. A k value of 11 or 12 does not degrade the performance of the signal chain. However, by fine-tuning the formulas, you can achieve optimum performance with lower k values.
Evaluating the charge-bank circuitry
In the circuit of Figure 6, the charge on CIN follows the input voltage before and after the internal ADC sampling switch, S1, closes. With this condition in mind, the timing evaluation ignores the influence of RIN. Figure 7 shows the model of a new SAR-ADC system. In this system, capacitors CIN and CSH have different initial voltages. At the start of a conversion, the charge quickly redistributes between CIN and CSH through RS1.
Figure 8 shows a simplified circuit for the capacitive input stage of the circuit in Figure 7. Before the input-signal acquisition, S1 is open (Figure 8a). The input capacitor, CIN, has an initial voltage of VIN, and the voltage across the sampling capacitor, CSH, equals VSH0. S1 closes at the start of signal acquisition (Figure 8b). The capacitor voltages, VIN and VCSH, become equal (Figure 8c) as the charge quickly redistributes between CIN and CSH.
The following equations calculate the charge on capacitors CIN and CSH:
QIN=CIN×VIN, (9)
And
QSH=CSH×VSH0. (10)
After S1 closes, the charge on CIN and CSH distributes between the capacitors. CIN and CSH combine into an equivalent capacitance, CTOT (Figure 8b and Figure 8c). The effective capacitance and charge distribution are:
CTOT=CIN+CSH, (11)
And
QTOT=QIN+QSH. (12)
Using equation 9 through equation 12, you can calculate a new equivalent voltage on capacitors CIN and CSH:
(13)
Introducing the ratio CIN/CSH=α, Equation 13 transforms into:
(14)
Now, you can calculate the required time constant of the input RC for the circuit in Figure 6.
(15)
where VTOT(t) is the voltage versus time across capacitor CTOT and VTOT(t0) is the voltage across CTOT at the start of the acquisition time, using Equation 14.
Again, to limit the error to ½ LSB, you must make the acquisition time long enough for the voltage on CTOT to approach the input voltage within ½ LSB.
(16)
Or
(17)
where VTOT(t0) is the voltage across the capacitor, CTOT, at the end of the sampling period. By changing VTOT(t) to VTOT(t0) and making equation 15 and equation 17 equal, you obtain:
(18)
and
(19)
Now, you can define a new way of calculating the time-constant multiplier, k3, using equation 14 and equation 19.
(20)
Equation 20 shows that k3 is a function of not only the initial charge, VSH0, but also the external capacitor, CIN. In the ADS8361, a 16-bit SAR ADC with a lower input-frequency signal of fIN≤fS/10, CSH’s calculated initial charge, VSH0, is half of the full-scale range. On the other hand, with the multiplexed signal at the input to the converter, you must use VSH0=0V. With these assumptions, Equation 20 becomes:
(21)
Table 2 shows how k3 changes as a function of CIN and shows lower valued time-constant multipliers, k3, for Figure 6’s 16-bit SAR ADC.
Test results
Figure 9 shows the results for the ADS8361, a 16-bit converter, tested in the configuration in Figure 6. The results show that the ADS8361 maintains good performance with SNR, SFDR (spurious-free dynamic range), and SINAD (signal, noise, and distortion) until k3 becomes smaller than six. This result differs from the k1-multiplier values of 11.1 and 11.78 that Table 1 generates. In Figure 9, the 16-bit ADS8361 SAR ADC operates at 200k samples/sec (tAQ=3.4 μsec). The frequency of the input signal is 10 kHz. In Equation 20, the initial voltage on VSH0 is equal to half the full-scale range. The value of the sampling capacitor, CSH, is 25 pF, and the value of CIN is 2.2 nF. With these assumptions, Equation 20 becomes:
(22)
(23)
and
(24)
Note that, in Figure 9, the improvement in SFDR is approximately 5 dB.
A little RC finesse helps
The following equations illustrate the key design guidelines for the SAR-ADC input circuits in Figure 6.
(25)
For multiplexed signals, this equation is:
(26)
And, for lower-input-frequency signals,
(27)
where α=CIN/CSH.
To maximize the system’s SNR, the value of CIN should be as large as possible with the op amp’s driving capability in mind. For preservation of the ADC’s THD, CIN should be either a ceramic device with a chip-on-glass dielectric or a silver-mica unit with ≤5% tolerance. The value of RIN depends primarily on the acquisition time, the value of CIN, and the op amp’s driving capability. RIN isolates amplifier IC1 from load capacitor CIN, which, for low-noise performance, should be a metal-film device with ≤1% tolerance. The RC filter between the op amp and the SAR ADC may compromise the amplifier’s stability. Reference 5 provides more details on op-amp selection and stability.
Acknowledgement
The authors wish to express special thanks to Art Kay, a senior applications engineer for Texas Instruments, for his help in developing the concept discussed herein.
References
· Oljaca, Miroslav, and Justin McEldowney, “Using a SAR Analog-to-Digital Converter for Current Measurement in Motor Control Applications,” Texas Instruments Application Report SBAA081, October 2002.
· Downs, Rick, and Miro Oljaca, “Designing SAR ADC Drive Circuitry, Part I: A Detailed Look at SAR ADC Operation,”AnalogZone.
· Oljaca, Miroslav, and Brian Mappes, “ADS8342 SAR ADC Inputs,” Texas Instruments Application Report SBAA127, January 2005.
· Downs, Rick, and Miro Oljaca, “Designing SAR ADC Drive Circuitry Part II: Input Behavior of SAR ADCs” Texas Instruments, 2005, AnalogZoneAcquistionZone.
· Green, Tim, “Operational Amplifier Stability, Part 6 of 15: Capacitance-Load Stability: RISO, High Gain, and CF Noise Gain,” Texas Instruments, 2005, AnalogZone, Acquistion-Zone.
· Baker, Bonnie, “Charge your SAR-converter inputs,” EDN, May 11, 2006, pg 34.
Author Information
Bonnie Baker is a senior applications engineer at Texas Instruments and has been involved with analog and digital designs and systems for nearly 20 years. In addition to her fascination with circuit design, Baker has a drive to share her knowledge and experience and has written more 250 articles, design notes, and application notes. She writes the column “Baker’s Best” for EDN.
Miroslav Oljaca is a senior applications engineer for Texas Instruments with more than 20 years of design experience in motor control and power conversion. He supports high-precision linear products for industrial applications. He received bachelor’s and master’s degrees from the University of Belgrade, Yugoslavia; holds more than 18 international patents; and is a member of several technical societies.
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