High performance synchronization designs in transmission systems

Network synchronization and clock generation are important aspects of a high speed transport system design. In order to improve the efficiency of the network by reducing transmit and receive errors, the quality of clocks that are used at various stages of the system should be maintained to specific levels. Network standards define the architecture of synchronization network as well as their performance expected at standard interfaces in order to ensure quality of transmission and the seamless integration of transmission equipments. There are a number of synchronization concepts and design aspects the system designer should be aware of while architecting the system.

Basic concepts: jitter and wander
A generic definition of jitter can be as "the temporal displacement of an event from its ideal occurrence." In digital transmission systems, Jitter is defined as the short-term variations of a digital signal's significant instants from their ideal positions in time. Assuming the event to be E, the nth time of occurrence can be considered tE[n]1.Figure 1, with the signal edges moving periodically around the ideal signal edge, depicts the concept of jitter.
The instantaneous jitter can be represented as:


Wander is low frequency jitter or it can be described as frequency jitter. A typical line of separation between the two is 10Hz. The effects that are created with jitter and wander are on different and specific areas of the transmission system.

Figure 1: Jitter illustration.

Jitter & wander measurements – TIE, MITE and TEDV2
Time interval Error (TIE) is the measure of interval that is provided by a real clock and the measure of that same interval by an ideal reference clock. At a given time t, the TIE of a clock generating time T(t) with a time interval called observation interval t, with reference to a clock Tref(t) is represented by the following equation. (x(t) is called the error function.)


Maximum Time Interval Error (MTIE) is defined as the maximum peak-to-peak delay variation of a given timing signal with respect to an ideal timing signal within an observation time (t=nt0) for all observation times of that length within the measurement period (T). It is estimated using the following formula:


MTIE is associated with slow variation of clock or wander. MTIE is measured whenever long term characteristics of the clocks are needed to be analyzed. MTIE value is a measure of the long term stability of a clock signal.

TDEV is another statistical parameter, a measure of the expected time variation of a signal as a function of integration time. TDEV can also provide information about the spectral content of the phase (or time) noise of a signal. TDEV is a measure of short term stability and is useful in assessing clock oscillator performance.

Figure 2: Derivation of MTIE from TIE graph.

Causes of jitter & wander in high speed transport systems

The most common imple-mentation is of a synchronization clock architecture is a low frequency system clock running in the backplane and synchronized high frequency clocks generated at each transport cards. With typical PLL frequency multiplication, the phase noise on a clock increases by an order of 20*log (N), when multiplied by a factor of N. Moreover, jitter on the input reference of the PLL will increase the lock time or even the PLL may not lock in presence of excess input jitter. Using a higher speed differential clock in the back-plane will give an increased jitter performance over a low speed single-ended clock.

Power supply noise is a major factor which could increase the clock jitter since the VCOs are sensitive to their input voltages variations. The output clock jitter amplitude is proportional to the power supply noise amplitude, VCO gain and inversely to the noise frequency3. The power or ground bouncing due to the resistive drop because of wire resistances and inductive noise due to wire inductances causes similar effects on the output clock jitter as described above. Providing an adequate power supply filtering on the system boards and appropriate decoupling capacitors closer to the power supply pins of the integrated circuits ensure a higher jitter performance for PLLs. Component thermal noise, the VCO technology used and the VCO gain, all affects the output jitter.

While transmitted across a distance, there are number of points in the transmitter and the receiver where the jitter gets accumulated. In the transmitter physical layer implementation, non-linearities such as DAC non-linearity or laser non-linearity could add to the signal distortion. On the transmission media and the receiver, apart from the spurious external sources (mostly on copper), fiber dispersion due to different frequency and modulation effects, signal dependant phase deviation due to receiver implementation (mainly bandwidth related) and clock extraction circuit implementation could add to the jitter in the signal stream.

Specific to SDH (synchronous digital hierarchy) transmission, there are a number of system level events that cause jitter. In a typical transmission system where a PDH (plesiochronous digital hierarchy) tributary is mapped on to SDH frames and transported across the SDH NEs (network elements), there will be resynchronization of the VCs (virtual container) at each intermediate node before the PDH tributary gets de-mapped at the terminating SDH de-multiplexer. Gapped clocks are used to map and de-map tributaries to STM-N frame, inhibiting the pulses corresponding to overheads, fixed stuff and justification bits, causing mapping jitter. The method of using justification opportunity bits to compensate for the frequency offsets in the PDH tributaries cause waiting time jitter. Pointer justification mechanisms compensating the phase fluctuations between the input VCs from the originating NEs and output STM-N frames generated locally, causes the VC extraction points to see abrupt changes in bit flow, resulting in the type jitter called the pointer adjustment jitter.

Effect of jitter on transceivers
Ideally, the digital signals are sampled at the midpoint of the two adjacent level transition points. Jitter results in bit errors as it alters the edge transition points of the signal with respect to the ideal midpoint. Error could be caused because of the edges of the signal stream varying too late (0.5UI (Unit Interval is equivalent to one period of the signal) later than the ideal midpoint in time) or too early (0.5UI earlier than the ideal midpoint in time.) When the sampling edge of the clock misses the signal stream by 0.5UI on either side, there is a 50% probability of bit errors happening, assuming a 0.5 average transition density.4

Effect of wander in transceivers
Receivers generally implement elastic buffers to accommodate the random fluctuations in the line signal as illustrated in the following block diagram. The recovered clock drives the data in to the elastic buffer and the system clock clocks out the data into the core of the device.

Figure 3: Receiver interface of typical transport system.

In synchronous transmission systems in slave mode, the system clock is usually synchronized to the recovered clock for interfaces receiving a higher timing level signal. The instantaneous as well as accumulated differences between the phase and frequency of the recovered and system clock will be absorbed in the elastic buffer or it will cause the elastic store to overflow or under-run resulting in pointer adjustments. Pointer adjustment mechanisms will advance or delay the position of payload in a transmission frame thereby adjusting the frequency and phase variations in the receiving and system timings. There are smaller buffers in the SDH transceivers compared to the PDH transceivers and there are limitations on the nature of irregularities like pointer movements that can
be caused on the SDH system. Therefore there are stringent requirements of synchronization compared to PDH systems.

Wander is generally measured in terms of MTIE, which provides peak time variation of a clock with respect to an ideal known reference. The application of MTIE value is in the design of elastic buffer in the synchronous transmission and switching equipment. In elastic stores, the buffer fill level is proportional to the MTIE between the input digital signal and the local system clock. Ensuring that the clock is compliant with the timing specifications in terms of MTIE, guarantees that certain buffer thresholds can not be exceeded. Therefore, in buffer designs, the dimensions are according to the specified limit of MTIE.

Effect of system clock output phase disturbances on transceivers
The output phase variation on a clock with respect to an ideal reference is determined by analyzing the MTIE information. Other than wander generation, the output clock phase is also affected by a number of system irregularities. Specifically to a system synchronizer, switching the reference source from a bad or impaired reference to a normal reference may cause output phase disturbances. Traditional VCOs implementing high speed PLLs for transmission employs the method of switching capacitor banks when reference clocks are changed.

The switching transition causes temporary phase excursions on the output clocks5. There are superior low jitter clock multiplier implementations which get around this problem.
High performing network clocks employ a mechanism called "holdover" when all the references to the system are lost, by generating last known good reference to the system by memory storage techniques. Entry and exit from the holdover modes might cause phase disturbances at the output. While in the holdover mode, due to the inaccuracy of reproducing the exact frequency, the output phase error continues to build. Improvements in integrated circuit technology have made the holdover accuracies as high as 0.01ppb. The impairments in the input reference and infrequent maintenance testing done on the system (which does not cause a reference switching) also cause output phase disturbances.

Occasions where the output phases are disturbed, keeping the magnitude and rate of phase error within the limits suggested by the standard bodies ensures that the degradation in the signal is taken care within the end to end system and there are no data corrupted or lost. For example, when the system synchronizer makes a reference switching, if the output phase error is stayed within the specifications, the synchronizer makes a "hitless" reference switch, indicating that there are no buffer overflows
or under-runs causing pointer movements, bit justification or slips.

Conclusion
Network synchronization and clock generation is the most important part of all high speed transport network systems. This paper describes the different types of clock impairments, mainly jitter and wander. The paper also details the causes of these impairments and how it affects the transmission system. Systematic design and implementation of the clocking subsystem leads to improved performance of the overall system, in terms of reduced bit error rates and ease of integration providing higher quality and efficiency of transmission.

References:

• Maxim High-Frequency/Fiber Communications Group Application note, "Jitter in Digital Communication Systems, Part 1," Rev 0; 9/01.


• ITU – T Recommendation G.810 (08/96) "Definitions and terminology for synchronization networks."


• Payam Heydari and Massoud Pedram, "Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops," IEEE Custom Integrated Circuits Conference (CICC), Orlando, FL, May 2000.


• Maxim High speed interconnect application note, "An Introduction
  to Jitter in Communications Systems," Mar 06, 2003.


• Simon Skierskan, Hazem Abdelmaguid, Gordon J. Reesor, Youcef Fouzar, Emanuil Huluta, Ranjit Singh, "Selecting the Right Clock-Circuit Topology for Low-Jitter SONET/SDH Applications," Zarlink Semiconductor White paper May 2003.

Author information
Ullas Kumar is an Applications Engineering Manager - Asia Pacific with Zarlink Semiconductor. He holds Masters Degree in Electronics Design from the Indian Institute of Science, Bangalore, India. He may be reached at Ullas.Kumar@Zarlink.com