Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed chip architectures, and Cadence Design Systems, Inc., the leader in global electronic-design innovation, have announced fully integrated and independently verified PCI Express solutions. The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.
The result of the joint work provides SOC designers with an independently verified solution that seamlessly integrates Rambus' design IP with the automated verification IP from Cadence. This solution helps shorten time to market with an efficient, predictable, and low-risk SOC design and verification to enhance the quality of the end product. In addition, the solution includes the Cadence Compliance Management System (CMS) featuring a PCI Express compliance verification plan (vPlan) and compliance tests, both of which have been specifically customized to the Rambus design IP. The CMS provides an automated plan and metric-driven solution to reach high levels of coverage without the need to develop tests. Based on the Cadence Incisive Plan-to-Closure methodology, the offering allows customers to maximize design quality while minimizing protocol expertise and verification time.
"As a company developing cutting-edge technology, it is critical that we build our solutions on proven, tightly integrated technology," said John F. Brown, vice president, Engineering at Tilera Corporation. "Using the combination of the Rambus configurable PCI Express Digital Controller with the independently developed verification IP from Cadence enables the rapid and successful IP integration we are looking for."
"Through this collaboration, we are able to provide an ideal combination of Cadence verification IP and methodology expertise with Rambus design IP. This solution leverages the strengths of both companies, speeding up the IP integration process and increasing productivity and quality for customers," said Steve Glaser, vice president of Marketing at Cadence's Verification Division. "Designers will gain a higher degree of predictability with the functional coverage provided by the Rambus design-IP-specific CMS. The result gives our mutual customers confidence that they will get to market on schedule with a quality product."
The PCI-SIG-compliant and interoperability-tested Rambus PCI Express solution has been implemented and shipped in numerous high-volume applications. Rambus digital core IP has adaptable application interfaces that minimize the amount of glue logic required for integration. Rambus PHY cells are delivered as complete serial communication cells, optimized for maximum production yield.
"Increasingly powerful computing and consumer electronics applications require IP solutions that are flexible and seamlessly integrate into our customers' designs," said Tim Messegee, vice president of Marketing at Rambus Inc. "With this collaboration, Cadence and Rambus continue our commitment to provide the market with superior integrated IP and EDA solutions that accelerate time to market and reduce design risk."
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