Altera Corporation has the FPGA industry’s first full-compliance support for high-performance DDR3 memory interfaces. Under the ratified JESD79-3 JEDEC DDR3 SDRAM Standard, Altera’s Stratix III family of FPGAs provides designers with the high-performance and low-power benefits of DDR3 memory that are becoming increasingly critical for a wide range of communications, computing and video processing applications.
These applications process large amounts of data that require quick and efficient access for optimum memory performance. Compliance with the JESD79-3 JEDEC DDR3 SDRAM standard meets the 1.5V, low-power supply voltage of DDR3 memory, which provides about a 30 percent system power reduction, faster performance and increased memory density for next-generation systems, while maintaining software compatibility with existing DDR applications.
Stratix III FPGAs support read and write leveling functionality embedded directly into the I/O element. This helps ensure compliance with the JEDEC write leveling requirement and corrects alignment of data reaching the FPGA fabric. DDR3 DRAM makers Elpida, Micron, Qimonda, Samsung and Hynix have all qualified various speed and density DDR3 memory devices for subsequent end-product use.
Altera,www.altera.com
