Power – too much of it – has been a recurring theme at this year’s Design Automation and Test Europe (DATE) show in Munich.
Both keynote speakers, from Samsung and IBM, referred to power as one of the major barriers to successful chip design, and several EDA companies were showing tools to help solve the problem.
In his keynote, Jeong-Taek Kong, VP of corporate CAD at Samsung Semiconductor, said: "For future mobile phones such as 4G, we need 100 times the performance. … This can only be achieved by system-on-chip."
More advanced process technologies such as high-k dielectrics, metal gates and Finfets can help achieve this, but design productivity, power and manufacturing are obstacles, he said.
"In the nanometer technology era, design for manufacturing, low power and ESL [electronic system level design] become the challenges of the entire semiconductor industry," Kong explained.
Meanwhile, second keynote speaker Garry Hughes, VP of foundry and ASIC services at IBM, looked at some of the details. "We’re now looking at single digit numbers of atoms in the gate oxide thickness. One atom off either side leads to a huge variation in performance and leakage. With CMOS everything leaks like it’s a bipolar circuit," he said.
Solutions exist such as multi-voltage islands and power supply gating, but these require extra logic. "It’s very, very complicated to get this done right," Hughes pointed out.
One of the newer companies providing tools to help reduce the power in advanced processes is Apache Design Solutions. "Supply voltage is dropping, so each millivolt of noise becomes a bigger percentage of the total," pointed out Keith Mueller, VP of sales and marketing at Apache.
Switching the power supply to an area of logic or memory can have unintended consequences, dragging down the supply to neighboring logic due to IR drop.
What is missing from EDA, said Mueller, is dynamic power analysis to model these transient effects, although other firms claim to have this capability.
Apache’s RedHawk tool takes on the dynamic analysis task. After extracting RLC data, the tool can add decoupling capacitors within the chip layout to reduce the effects of IR drop.
"It used to be that the guardbanding you did was enough," said Mueller. "But at 90nm and below, this [decoupling] is a requirement."
However, Vic Kulkarni, president and CEO of rival company Sequence, pointed out that adding decoupling capacitors (decap) is causing its own problems by adding considerably to leakage power at advanced process nodes.
"Leakage is increasing at 5x per technology node. At 90nm, 40 percent of power is leakage," Kulkarni said. "These are intrinsic problems of solid state physics."
He does agree that dynamic voltage drop analysis is one answer: "There’s a new opportunity in a power aware flow. You need to think of power at all levels of abstraction."
Both Mueller and Kulkarni agreed that the earlier in the design flow power was considered, the greater the savings that can be achieved in the final design.
