Extending the company’s industry-leading solutions for saving power at the chip and system levels, Actel Corporation has rolled out its Libero Integrated Design Environment (IDE) with significant new features, such as power-driven layout, that enable designers to further optimize designs to reduce dynamic power consumption by as much as 30 percent for a typical design. With the advanced power analysis capabilities built into Libero’s SmartPower tool, the enhanced analysis environment is the first to give users a comprehensive understanding of power usage in all functional modes of the design. In addition, an innovative battery life estimation feature gives portable designers an accurate calculation of battery life based on their FPGA design power profile — a first for field-programmable gate array (FPGA) design tools.
The new version of Libero supports all of the company’s low-power families, including the ultra low-power Actel IGLOO FPGAs and the mixed-signal Actel Fusion Programmable System Chips (PSCs).
Power-Driven Layout Reduces Dynamic Power by as much as 30 Percent
A new option in Libero actively utilizes SmartPower's design analysis data for power-driven layout, which enables users to quickly realize dynamic power savings through the reduction of the capacitive loading of the nets. While average IGLOO power consumption is reduced by 13 percent, some designs can reduce consumption by as much as 30 percent.
Battery Life Estimation Aids Designers of Portable, Battery-operated Applications
With Libero IDE v8.1, SmartPower provides designers the ability to create power profiles to help estimate necessary power supply and battery requirements. Defined by the user, the power profile is the percent of time the FPGA will be in a combination of custom or functional modes, such as Active, Standby, or Flash*Freeze. To provide battery life estimation for portable or handheld designs, for example, the user inputs the desired battery’s current capacity as well as the power profile of the FPGA. SmartPower then displays the expected battery life as well as a realistic and accurate report of power consumption based on the true power profile of the target FPGA.
Enhanced SmartPower Analysis Enables Power Efficiency in Portable Designs
The Libero IDE v8.1 also features enhanced SmartPower functionality, which enables analysis of the entire FPGA as well as specific portions of the device or design, such as clock domains, switching cycles, and spurious transitions, which individually contribute to overall power consumption of the device. A cycle-accurate power analysis option, for example, allows designers to look at peak power per clock cycle as well as the average power for the entire simulation.
The switching analysis option in the SmartPower tool identifies “hazards,” or spurious transitions, that contribute to higher power consumption, allowing the user to address them and make corrections to reduce the power consumption. In a typical design, hazards can account for as much as 20 percent of the power consumed. In some circuits, such as combinational adders, the power dissipation caused by spurious transitions can be as high as 70 percent of the total power.
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