The MAX II CPLD family from Altera (www.altera.com) features an internal oscillator that dissipates much lower power than do external oscillators. The internal oscillator has an accuracy of only ±25%, sometimes limiting its usage. For example, many applications, such as an interval timer for data gathering and a real-time clock, require more accuracy—±0.1 and ±0.001%, respectively. A simple circuit uses an external crystal oscillator to calibrate a timer to better than ±0.3% accuracy. The internal oscillator sustains the calibrated output even after you shut down the external oscillator to save power. The circuit maintains this accuracy as long as the VCC and temperature are stable. Whenever you enable the external oscillator, the circuit quickly recalibrates if necessary.
A remote industrial sensor should sample an event every second. To save power, a timer powers down most of the sensor circuit most of the time to increase battery life. The system powers up for a short sample; then, the system, except for the CPLD, powers down, which times the period to the next power-up, sample, and calibration. Most of the components of a wireless receiver in a power-saving mode power down; however, the CPLD timer and wake-up mode stay on for monitoring and calibration.
Figure 1 shows a simple circuit with a crystal oscillator with typical ±100-ppm accuracy; an EPM240 CPLD with a ±25%-accurate, 4.4-MHz internal oscillator; and an autocalibration circuit in the programmable-logic array that generates a ±0.3%-accurate, 10-kHz clock. For simplicity, the figure omits the external oscillator’s VCC1 power-down or enable circuit and the application logic using the 10-kHz clock. The 33.33-MHz clock drives a reference counter, which is a divide-by-3333 LPM (library-of-parameterized-macros) counter. You derive LPM blocks from Altera’s Quartus II LPM. The COR (carry-out-reference) signal feeds back to the count-enable input such that the COR signal stays at one after reaching the 3333 count until you apply the reset signal. The divide-by-3333 counter generates a 0.1-msec reference period. The 4.4-MHz LPM oscillator drives all other clocks in the autocalibration circuit: the source counter, a 10-bit counter with a power-up asynchronous reset; a synchronous reset; and a 10-bit output source. The 4.4-MHz clock also drives the 10-bit up/down-adjust counter that presets to 333 at power-up. It has an enable input, an up/down-control-input signal, and a 10-bit output adjustment. The adjust and source drive the inputs of the compare LPM that generates a one on the COC (carry-out-from-comparator) signal when adjust equals the source. The COC signal drives the synchronous input of the source counter, making it a free-running counter with a period equal to the adjustment signal. An LPM register converts the COC signal into a synchronous, 10-kHz pulse when you calibrate the system. The control-logic block generates enable, up/down, and synchronous-reset output signals based on the COC and COR inputs.
Figure 2 shows the operation of the control-block state machine. It also illustrates how the 10-kHz signal calibrates to the oscillator input. The system powers up in the start state, and the source and reference counters both start counting. Adjust starts at 333, the minimum count that the slowest variation of the LPM oscillator would require to generate a 10-kHz clock. The COR signal typically goes high before the COC signal. This action moves the state machine to the slow state, enabling the adjust counter in the up mode. It counts up from 333 until the source equals the reference, removing most of the difference between adjust and the value necessary to achieve calibration. Once the source equals the reference, the state machine moves to the calibrate state. Calibrate disables the adjust counter and resets the reference counter. The free-running source counter resets at the same time.
The COR signal will likely occur again before the COC signal and will repeat the last sequence. Eventually, the COC signal will happen before the COR signal, moving the state machine to the sustain state. In this state, the adjust counter is disabled. Once the COR signal goes high, the COC signal comes around again, making the COC and COR signals ones. The state machine then goes to the fast state. Fast enables the adjust counter in the down mode, resets the reference counter, and then goes to start. The free-running source counter resets at the same time.
When you calibrate the circuit, the COR and COC signals occur at the same time, and the state machine goes to the calibrate state. The adjust counter remains constant, the source counter resets, and the state machine moves to start. Meanwhile, the free-running source counter resets. The system stays in this calibrated loop with an occasional cycle through slow or fast to make minor adjustments to the adjust counter. If the external oscillator stops, the COR signal stays low, resulting in the state machine’s staying in the sustain state until the external clock starts again. In the sustain state, the 10-kHz output stays constant assuming no significant change in system temperature or VCC.
The following equations set the reference-count, adjust, and source-counter bit width; the adjust-counter start value; and the output-frequency accuracy: Adjust and source bit width=log2(5,555,555/output frequency) rounded up; adjust-start value=3,333,333/output frequency; reference-counter period=external-oscillator frequency/output frequency; output-frequency error=±1%/(3,333,333/output frequency); maximum output jitter=±1/3,333,333 sec; and maximum calibration time=output frequency×5.
You can achieve accuracy better than ±0.3% with a slower output frequency, but it cannot exceed the accuracy of the external oscillator. Therefore, you can build a real-time clock with a 0.01-second resolution and ±0.003% accuracy.
Captions
Figure 1 This internal CPLD counter first synchronizes with an external clock to 60.3% accuracy and stays at that frequency until reset.
Figure 2 This state machine shows the transitions of the control block in Figure 1.
