Xilinx teams with EDA leaders to tackle ultra high-capacity FPGA design verification
( 01 Jan 2008 )
Xilinx announced a collaboration with the industry痴 leading EDA companies to address the challenges of ultra-high capacity FPGA design verification. The company痴 engineers will be joined by Cadence Design Systems, Mentor Graphics Corporation, and Synopsys to define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today痴 65nm FPGAs as well as new and emerging FPGA architectures. The collaboration will focus on expanding coverage, improving simulation runtime, and reducing verification time in an environment that allows designers to achieve aggressive design goals. Major releases of these tools and methodologies are expected in the first half of 2008.
