S3’s recent announcement of a library of mixed-signal IPs for TSMC’s 65nm processes has greater significance than what is apparent.
One of the common questions designers face is “Will analog scale?” Some designers often doubt whether analog will be needed in scaled technologies. For one thing, it is well known that analog cannot take advantage of technology scaling either in power or in performance, and hence is unable to give adequate economic benefits through scaling. Hence the trend for more and more analog functions moving over to digital functions. The availability of far better design automation tools for digital than for analog is yet another reason for the digital design boom.
REAL WORLD IS ANALOG Undoubtedly digital circuits can provide tremendously efficient and cost effective storage and computing power, but they still need analog for interfacing to the real world simply because the real world is analog. As a result of this, complicated mixed-signal designs will always be there. This creates three main challenges: first, how to do system-level mixed-signal designs; second, how to verify system-level functionality after chip assembly; and third, how to ensure cost advantage in ultra deep nanometric range when a part of the chip is going to have analog designs.
While the solution for the first two problems lies mainly in creating appropriate tools, the third problem needs a techno-economic solution. SoC designers need to consider the cost of putting analog functionalities on the SoC versus the cost of putting them off the SoC but in the same package. Designers will generally consider it heroic to integrate both analog and digital in the same SoC. Such notions of heroism should be avoided. While integration would be a great technological achievement, it could reflect poor economic sense. Analog should be used in SoC only where it makes economic sense. Interestingly, increased digital processing has lead to architectures wherein digital processing can be used to improve analog performance. Take, for instance, the replacement of opamps in switched capacitor circuits with comparators. Such usages can help make innovative designs. Some designers say that this kind of innovation cannot go beyond 65nm, or if stretched to the maximum, beyond 45nm. Gate leakage with silicon dioxide gate dielectrics and increased 1/f noise with alternative gate dielectrics will limit such innovations in circuit designs. I, for one, would say that as of today these innovations are a great option for the designer, and I do not preclude the ability of technology to come out with solutions that can solve the perceived problems at lower nodes even as analog designs will continue to be restricted because of various factors, mainly high design costs, inferior tools, poor scalability compared to digital, and most of all because of difficulties in implementing them.
CHARACTERIZED SILICON The S3 announcement is based on characterized silicon and not on promising simulations. Among the IP blocks characterized at 65nm are 10-bit ADCs at 30 and 40 Msamples; a 11-bit, 160 Msample sigma-delta ADC; and a PLL. S3 confirms that the design methodology at 65nm was almost the same as that at 90nm, and the major difference was the increased activities around DFM in the design flow. S3 has achieved 66-67dB spurious-free dynamic range with a 65nm ADC. This should be enough to meet system requirements if noise can be judiciously managed across the entire signal chain.
However, the Company has cautioned that not all circuits could be ported successfully to 65nm. This could cause some concern to wireless vendors, whom S3 primarily targets. The greater noise sensitivity with some of the emerging wireless standards should make wireless vendors careful in choosing the right ADC.
The real import of S3 design IPs is that we shall see the familiar mixed-signal libraries at 65nm, notwithstanding predictions that scaling problems will bring about the end of mixed-signal designs at 65nm.
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