Altera Corp. has announced the winning design teams of its annual Nios II Embedded Processor Design Contest. First prize winners include design teams from Beijing Jiaotong University in China; I-Shou University in Taiwan; National Institute of Technology, Trichy, in India; and Inha/Hongik Korea Aerospace University in Korea. The winning teams displayed their innovative designs at Altera’s recently held SOPC World 2007, which took place in different venues throughout Asia Pacific.
Conducted through Altera’s University Program, the Nios II Embedded Processor Design Contest provides design-engineering students throughout Asia Pacific with hands-on programmable logic and embedded processor design experience in preparation for real-world advanced system design. The 2007 contest attracted 733 entries with 20 teams receiving awards totaling US$20,000.
A new award was introduced this year for the creative use of the Altera Nios II C-to-Hardware Acceleration Compiler (Nios II C2H Compiler). This productivity tool substantially increases the performance of embedded software by automatically converting performance-critical C language subroutines into hardware accelerators and integrating them into FPGA-based Nios II subsystems. Recipients of this award included design teams from Chongqing University in China and Inha/Hongik Korea Aerospace University in Korea.
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