Stratix III FPGAs achieve 533MHz DDR3 interface performance
(Technology News, 18 Dec 2007 )
Altera Corp. has achieved DDR3 memory interface speeds in excess of 1Gbps with its Stratix III FPGAs, providing a 33 percent advantage in memory performance over competing FPGA solutions. This higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks.
Altera’s Stratix III FPGA family is claimed to be the industry’s only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.
In addition to higher memory interface speeds, Stratix III FPGAs demonstrate 29 percent lower power consumption and a 25 percent performance advantage, as compared to competing solutions, making the device family ideal for high-performance applications that require the lowest possible power.
Designed to address the benefits of DDR3 memory, Altera’s Stratix III family include read and write leveling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations. In addition, Altera’s Quartus II software version 7.2 includes a DDR3 PHY wizard and controller intellectual property (IP), which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.
