Micrel announces new LVPECL/LVDS, ultra-low jitter clock dividers
(Product News, 09 Jan 2008 )
Micrel Inc. has added four new divide-by-three and divide-by-five clock dividers to its clock divider product family. The SY89228/229 are 1GHz LVPECL/LVDS dividers that feature Fail Safe Input (FSI) circuitry and the SY89230/231 are 3.2GHz LVPECL/LVDS dividers. Targeted applications include pre-scaling functions, PLL clock generation and distribution, RF transmitters, and wireless base stations.
“These new divide-by-three and divide-by-five clock dividers are the only clock dividers that divide 'odd' numbers and provide 50 percent duty cycle currently on the market,” said Thomas S. Wong, Vice President, High Bandwidth Products, Micrel. “The SY89228/229 offer our very own FSI feature, which provides a simple, integrated, transparent solution for hot swap or failed input conditions. This is particularly important for the prevention of unstable output conditions in rack-based equipment that must continue to operate while servicing I/O cards.”
The SY89228U and SY89229U, along with the rest of the FSI family of solutions, are optimized to prevent unwanted oscillations and maintain output stability when an input signal’s swing collapses or disappears. Unlike existing LVPECL or LVDS dividers currently on the market, Micrel’s FSI family prevents a metastable output condition when the input signal is removed or the amplitude fails. This is especially crucial for rack-based equipment that has many I/O cards requiring Hot Swap capability. In addition, the SY89228-231 divider product family offers Micrel’s patented 3-pin internal input termination, which simplifies designs and interfaces to any differential signal, AC- or DC-coupled, without any level shifting or termination resistor networks in the signal path.
The devices are offered in an ultra-small 16-pin MLF package that saves critical space while providing excellent performance.
