Xilinx teams with Helion to deliver enhanced security for low-cost FPGAs
(Business News, 17 Jan 2008 )
Xilinx has announced that it has teamed with data encryption IP specialist Helion Technology to enhance the security features in the Xilinx Spartan-3 generation of low-cost FPGAs. The new Helion intellectual property (IP) cores c leverages Xilinx innovative DeviceDNA design security solution to further streamline and strengthen safeguards against reverse engineering, cloning, and unauthorized overbuilding. Xilinx Spartan-3 FPGA-based solutions are on display this week in Xilinx booth #35768, located in the South Hall.
According to industry analysts, companies lose over $500 billion in lost sales every year as a result of counterfeit products. This threat grows by more than 12 percent per year, tarnishing the reputation and long-term credibility of genuine brands. “Device security is a critical aspect of today’s complex devices. Implementing design safeguards should not be a major time sink for designers. With the latest version of our security solution, we provide a robust and flexible approach that can be quickly implemented,” said Kevin Kitagawa, director of High Volume Marketing at Xilinx. “The additional features added by the Helion IP further strengthen our solution without making it intrusive or requiring compromises in design size or development time.”
Streamlined Approach Xilinx first introduced its revolutionary DeviceDNA technology, a permanent factory-set ID code that is different in every device, with its low-cost Spartan-3A FPGAs. Leveraging its proven cryptographic IP and expertise, Helion has developed IP that enables designers to easily implement the Xilinx DeviceDNA technology in their designs. The Helion approach uses a selection of cryptographic functions to implement the security algorithm and various obfuscation techniques, ensuring that any reverse engineering attacks on the design are made suitably difficult. Most importantly, the IP is highly parameterized allowing each user to make their implementation unique, thus preventing others using the same IP from working around the security scheme.
Helion DeviceDNA Checker Helion’s DeviceDNA Checker has relatively low resource requirements and a simple interface, so that it can be easily dropped into the user design alongside the main FPGA application. The checker uses input from the DeviceDNA block in the FPGA plus other stored values to initiate processing and subsequently generate a “pass/fail” flag. This flag can be used to degrade normal operation of the rest of the design if the check does not pass.
The DeviceDNA Checker uses the DeviceDNA code, plus additional check bits that are stored in non-volatile system memory to enhance security. These bits are a mixed up combination of randomly generated bits that form part of the check algorithm, randomly generated bits that are ignored, and the final stored check code itself. The additional data is simply streamed into the checker after the DeviceDNA bits.
