Promising technologies for 32nm generation system LSIs and beyond
(Top News, 18 Jan 2008 )
Toshiba Corporation has achieved breakthroughs in three major basic technologies for 32nm generation system LSIs and beyond. The advances are a major advance in metal gate electrode; a new structure and process technology for low resistance contacts that reduce contact resistance; and a technology for improving performance by changing the surface orientation of the silicon substrate. These breakthroughs will pave the way to 32nm LSIs and improve process efficiencies.
In developing the improved, new metal gate, Toshiba realized a simplified manufacturing process technology that employs nickel silicide, a common material for both nMOS and pMOS transistors in a ratio of 1:3, respectively, and introduces an aluminum layer only in the nMOS gate.
For the low resistance contact, Toshiba employed a metal material in the source/ drain region, reducing contact resistance to a quarter in the nMOS side. The base electrode material is the same for both the nMOS and pMOS in pairs, and low-Schottky-barrier metal suitable for each type MOS transistor is segregated at interface of base material. The manufacturing process is simplified.
System LSI integrates CMOS elements, nMOS transistors and pMOS transistors. Therefore an optimized process is required. These new two technologies enhance performance and also contribute to an efficient manufacturing process.
The technology for changing the surface orientation of the silicon substrate rests on the fact that using the (110) surface improves hole mobility as compared to the usual (100) surface. Toshiba found that both carrier mobility and gate capacitance increase in the (110) pMOS FETs, and demonstrated further improvement of drive current by 19% in a 32nm generation embedded-SiGe source/drain structure with 0.6% strain. In addition, the company found that the (110) pMOS FETs achieves a six-times faster processing speed in ideal conditions.
