by Oh Sung-Chan, Senior Field Application Engineer, Altera, Korea
Any user who has experience in using programmable logic devices (PLDs) should have heard of Altera’s MAX series or FPGAs. Like most semiconductor companies, Altera is continuously developing and providing high performance, low cost PLDs. Altera’s structured ASIC solutions are based on FPGAs. This article focuses on the technical aspects of the company’s HardCopy II.
Architecture
HardCopy is a solution that enables customers to migrate their designs created and verified on FPGAs to low cost ASICs. It consists mainly of Stratix HardCopy and HardCopy II linked with Stratix II. Figure 1 illustrates a Stratix II FPGA, die, and a corresponding HardCopy II. A bigger die is needed in FPGAs for logic of the same size due to programmability. Programmability is removed in HardCopy, thereby decreasing the die size. Furthermore, power consumption is also decreased as the unnecessary parts of FPGAs are removed, and the power is disconnected from the cells not used in HardCopy.
HardCopy was developed from Apex HardCopy (0.15µm, TSMC) in 2001, and evolved into Stratix HardCopy (0.13µm, TSMC) in 2003.It progressed to HardCopy II (90nm, TSMC) in 2005 (Figure 2).
While the same architecture with FPGA (with only programmable circuitry removed) is used in Apex and Stratix HardCopy, a different HardCopy Cell (HCell) is introduced into HardCopy II for lower cost and increased usability. This supports more than simple 1 to 1 conversions, providing customers with freedom of choice.
Figure 3 shows the structure of a HardCopy device. It is made up of basic cells (HCells) that implement logic. Two types of embedded memories exist: MRAM and M4K, depending on the internal memory’s block size; and clock generating PLL and I/Os for input and output are assigned at each bank. While it is similar to the FPGA in many respects, the biggest difference is that the die size of a HardCopy is relatively smaller, enabling a significantly reduced power consumption.
Figure 4 details how the ALM (adaptive logic module), the basic cell structure of Stratix II FPGA, is converted into HCell, HardCopy II’s basic cell. If the RTL code targets the FPGA, a sequential logic is mapped to the REG block, while other logics are mapped into a Look-Up table on the left. And when it is converted into HardCopy at Quartus II, each block is converted again to HardCopy II’s basic cell units.
For detailed information on the structure and functions of HardCopy II devices, visit: http://www.altera.com/literature/hb/hrd/hc_h51011.pdf.
Differences
As mentioned earlier, HardCopy has many similarities with structured ASICs. However, unlike general structured ASICs, all the processes after verifying the design created on FPGA are performed at Altera’s HDCC (HardCopy Design Conversion Center), freeing customers from incurring additional costs. On the other hand, because the PCB used for existing FPGA verification needs to be re-designed due to change in package, the ASIC solution requires additional cost and time.
In the process of converting an FPGA design to ASIC, fundamental functions and timing performance should be verified again where new high price ASIC design tools different from those used in designing FPGA are required. For HardCopy, only the same Quartus II that is used for FPGA design is required, and users do not need to perform backend procedures thus removing the need for EDA tools.
In standard cell ASICs, all layers needed are made for each design (Figure 5). As process technology evolves, the cost for masking each layer increases resulting in higher cost for each layer manufacturing. However, in structured ASICs such as HardCopy, only the top metal layer is changed with most other layers commonly shared. This enables processing and manufacturing of wafers in advance without the metal layer. ASICs with different features can be produced if masks for metal layers of different designs are made and added to the already made basic layers.
HardCopy Design Flow
Converting an FPGA design into HardCopy involves the following process: First, an RTL code is generated, which can be synthesized into a logic circuit using Verilog or VHDL. The RTL code is then synthesized into the structure that fits the selected FPGA using Quartus II. The fitting of Quartus II places the synthesized (composed) logic circuit to FPGA cells and does routing of the cells. After the place and routing process, an internal analyzer analyzes the timing characteristics of the designed circuit’s clock and I/O pins. If all timing requirements are met, the FPGA is programmed using the generated programming file (*.pof) and verification starts (Figure 6).
In HardCopy family, the FPGA design could be converted to only one HardCopy device. But with HardCopy II, if a design is compiled with FPGA, an optimal HardCopy II device is selected for the resources used in the design (logic size, number of pins, memory size, etc.) (Figure 7). After this, the user selects a HardCopy device and generates a design database to be compiled for conversion to HardCopy using Quartus II.
When a design database for HardCopy is created and compiled in Quartus II, the existing design implemented on FPGA is changed to a HardCopy design. Once compilation is completed, a report file for HardCopy is created for FPGA that includes information on HardCopy resources such as timing information (Figure 8).
Despite the fact that Quartus II supports a variety of FPGAs, a HardCopy device can be also selected as a target device like an FPGA. Quartus II’s synthesizer can create netlists for HardCopy and FPGA out of a same design code, which have identical functions but use different cells.
Although compiling a design to Stratix II and converting it to HardCopy is the most commonly used method, users can also compile as HardCopy and then convert to FPGA. After synthesizing the design to FPGA or HardCopy using the dedicated synthesis tools such as Synplicity’s Synplify Pro, VQM (Verilog Quartus Mapping) is created and then compiled with Quartus II (Figure 9).
A HardCopy design flow has more constraints than FPGA design flow, and must be verified when converted to HardCopy, and because HardCopy is an ASIC solution, there are few options and therefore not easy to handle when a problem occurs unlike on FPGA (unless the weakness in design is checked and corrected in advance). For instance, many users who verify a design with FPGA use techniques such as gated clock (listed below), which can often directly influence operations like timing issues, even in FPGA and HardCopy. Design techniques listed below must be avoided when converting to HardCopy. Even in an FPGA design, those techniques are not desirable in order to prevent problems in advance.
See http://www.altera.com/literature/hb/hrd/hc_h51011.pdf for more detailed information on HardCopy design constraints (rules).
After all the verification processes are completed, the handoff files should be collected, made into a single file, and sent to Altera HDCC. This completes the procedure for a user to create HardCopy.
In general, an ASIC design flow is divided into two large parts: the process to create a design code, synthesize it into logic gates, and then verify timing and functions is the front-end process; while back-end process comprise various final verification steps of designer’s netlist before manufacturing, including layouts.
Unlike the front-end process, the back-end process is done at Altera HDCC. Once the files for HardCopy are delivered from a user, HDCC does a series of tasks related with HardCopy, as well as formal verification (Figure 10). If no problem is found, it performs the procedure to implement the netlist with real HardCopy device cells (place and route). This procedure is often called layout. When layout is completed, various parameters are extracted and verification tasks such as timing analysis and interference noise simulation are performed using these values. If the design goes though all the verification processes and the user finally confirms timing analysis, the final data is sent to a mask manufacturer (tape out).
In the process of HardCopy design, Altera and the user have three design reviews in total.
DESIGN REVIEWS The first design review is done while developing the FPGA, where checking the feasibility of conversion from FPGA to HardCopy is the main focus. The second design review is done just before the user’s final design is delivered to Altera HDCC. At this stage, timing constraints set by the user are verified for timing analysis. Quartus II’s Design Assistant is run to check design related warnings or error messages. After the design review is finished, HDCC starts conversion of the user’s design. Conversion generally takes about six weeks. The third and last design review is performed just before tape out to produce mask after all the back-end processes are done. Before this last review, the final timing analysis result of converted HardCopy is provided to the user. If the user checks and finally confirms (sign off), it is sent for the next step, which is production.
About six weeks later, a small number of HardCopy sample products are delivered to the user for test (Figure 11).
Author Information
Oh, Sung-Chan joined Altera Korea as FAE specialist in 2000, and is a enior field application engineer in charge of LG Electronics. Prior to joining Altera Korea, he worked at semiconductor division of Samsung Electronics Co., Ltd. as a SYSTEM LSI/ASIC designer from 1995 to 2000. He acquired a bachelor’s degree in Electronic Engineering from Chungang University in 1995.
Captions
Figure 1: Stratix II FPGA die and a corresponding HardCopy II.
Figure 2: The development of Hard Copy II.
Figure 3: Structure of a HardCopy device.
Figure 4: How the ALM (adaptive logic module) of the Stratix II FPGA is converted into HCell, HardCopy II’s basic cell.
Figure 5: Standard cell ASIC vs. structured ASIC.
Figure 6: Programming an FPGA.
Figure 7: A design database is compiled.
Figure 8: When a design database for HardCopy is created and is compiled in Quartus II, the existing design implemented on FPGA is changed to a HardCopy design.
Figure 9: Quartus II’s synthesizer can create netlists for HardCopy and FPGA out of a same design code.
Figure 10: Verification process.
Figure 11: Three reviews of the HardCopy design process.
