When designers were transitioning from 130nm to 90nm, and then from 90nm to 65nm, it was feared that the design rules would change so radically that engineers would have to acquire a world of new design experience to succeed at the new node. However, no revolutionary changes were necessary as designs went from 130nm to 90nm and further to 65nm. Now, with 45nm success stories emerging both from foundries and IDMs, no fundamental change in design rules has been noted even at 45nm. Indeed, some foundries say that designing at 45nm is so similar to designing at 130nm that those designers who have designed at 130nm but never at 90nm and 65nm can skip these design nodes and work directly at 45nm.
MOST IMPORTANT CHANGES
However, every node has presented some unique challenges that necessitated some design changes. The two most important changes at 45nm are the use of immersion lithography and ultra low-k materials. Earlier foundry designers would experiment with new materials in their quest for ideal k. When 130nm was introduced, new low-k and copper materials were used, which enhanced yield problems and failure rates. New tools had to be created to solve these problems, which helped the EDA industry but increased tool costs for customers. For the time being, foundries have not gone for new low-k materials. However, pilot materials are at an advanced development stage. TSMC, UMC, and CPTA (Common Platform Technology Alliance comprising of Chartered, IBM, and Samsung) have confirmed that mass production of these materials are on the horizon, and they have been working with EDA vendors to ensure that the latter can design tools to handle leakages.
When employing conventional materials at 65nm node, leakage accounts for 40 percent of IC total power consumption, forcing chip designers to use low-power design techniques. At 45nm leakage rises to as high as 65 percent of the chip power consumption. Thus, the need for power management becomes more challenging than at 65nm. Sophisticated power modeling and use of thermal modeling for 45nm tool flow are some of the proven techniques being used. Freescale, for instance, confirms that even as the transition from 65nm to 45nm is “non-revolutionary,” it has been using dynamic-voltage-frequency scaling, gate-retention power grating, and other power-management techniques more extensively at 45nm. The general approach adopted is to locate hot spots and intra-die thermal variation points, and identify the strongest points of power dissipation. IBM’s SOI is said to provide good improvement in power as well as performance over CMOS processes.
POWER SAVINGS
While some IDMs have used SOI, foundries are not convinced of its advantages and still offer CMOS. However, they are working extensively on power management at new ultra low-k processors and have involved EDA companies in creating tools to manage power at 45nm. For instance, TSMC has incorporated “enhanced low-power technique recommendation” in its 8.0 reference flow to help customers achieve greater power savings. For this reference flow, TSMC has also validated the Cadence-backed Common Power Format (CPF) that is under the aegis of Silicon Integration Initiative (Si2). CPF lets tools from across the design flow to work from a single power format.
TSMC has come out with a series of recommendations that are said to be tried and tested. These are: using advanced voltage scaling and hierarchical voltage with dual-power SRAM blocks to deal with dynamic-power management; using coarse-grained data retention and power gating with lower drain-to-drain voltage to minimize standby power leakage; using longer channels in non-critical paths to reduce active leakage; and using source- and back-biasing. These techniques are essentially about shutting down those blocks that are not in use. EDA companies, especially Cadence, Synopsis, and Magma, have introduced low-power commercial tools that have been qualified by TSMC, UMC, and CPTA, but what is required is an all-in-one power flow to run on 45nm, and all these three companies are working on it.
