Traditionally, digital logic has not consumed significant static power, but this has changed dramatically as process nodes have shrunk. Leakage current in digital logic is now the primary challenge for FPGAs as process geometries decrease. When power-reduction strategies are not employed, power consumption becomes a critical issue as static power increases dramatically at the 65-nm process node. Static power consumption rises largely because of increases in various sources of leakage current. Figure 1 shows how these sources of leakage current (blue) increase as the technology makes smaller gate lengths possible (green).
Power consumption is composed of static and dynamic power. Static power is the power consumed within an FPGA when it is programmed with a programmer object file (.pof), with no clocks operating. Both digital and analog logic consume static power. In an analog system, static power is primarily composed of the quiescent current of the analog circuit based on its interface configuration. The sources of static leakage current in 65-nm are shown in Figure 2 and Table 1.
Dynamic power is the additional power consumed through the operation of the device caused by signals toggling and capacitive loads charging and discharging. The main variables affecting dynamic power are capacitance charging, the supply voltage, and the clock frequency (Figure 3). Dynamic power decreases with Moore's Law by taking advantage of process node shrinks to reduce capacitance and voltage. The challenge increases when more circuits are implemented with each process shrink and the maximum clock frequency increases. While the power reduction declines for an equivalent circuit from process node to process node, the FPGA capacity keeps doubling and the maximum clock frequency keeps increasing.
Designing for Low Power and High Performance
Attacking these power challenges with innovative architecture and with the latest advancements in process technology and circuit techniques are the keys to conquering FPGA power consumption.
Having the capability to control and program power settings is an unprecedented method for reducing power in high-end FPGAs. Traditionally, high-performance FPGAs are implemented with a high-performance fabric where every logic element (LE) provides the maximum performance with a subsequent high leakage power. Being able to take advantage of most circuits in a design that have excess slack and therefore do not require the highest performance logic reduces power consumption.
Programming power settings enable the logic fabric of an FPGA to be programmed at the logic array block (LAB) level by providing high-speed logic or low-power logic, depending on which is required by the specific logic path (Figure 4). By doing this, the small percentage of circuits that are timing critical are “selectable” to a high-speed setting, with the remainder using a low-power setting, this can result in a 70% decrease in leakage power for the low-power logic. By placing unused logic, as well as digital signal processing (DSP) blocks and memory into the low-power modes, power can be further decreased. Being able to program power settings enable an optimal combination of high-speed logic to achieve the desired system performance while the remainder of the logic can be placed into low-power mode, thereby minimizing leakage current and resulting in the lowest power consumption.
Delivering the exact amount of high-speed logic requires a design to reach its desired performance while being controlled with a very high degree of precision. The programmability between high-speed and low-power logic is controlled on a per-tile basis (each tile containing two LABs, or a LAB and DSP block, or a memory block, all with associated routing). Controlling individual tiles as either high speed or low power on large FPGAs can achieve the lowest possible power for design development software. This includes specifying timing constraints to optimize the design when placing tiles into high speed or low power mode automatically.
Further having the capability of selecting the core voltage (0.9-V or 1.1-V) of the FPGA allows designers to maximize performance requirements of the design. A 0.9-V core voltage can provide an overall minimum dynamic and leakage power, while a 1.1-V core voltage can deliver the overall highest performance. Dynamic power scales with the square of core voltage while static power scales by the power of 2.5 of core voltage. Selecting core voltage input supplies all LABs, memories, and DSP functions in the core fabric, thus affecting fabric performance. When choosing a core voltage to use, a designer must take into account the system performance requirements reported from the timing analysis.
When combining the ability to program power settings and select core voltage, various performance and power operating points could realize a power reduction of over 50% at 1.1 V. The combined static and dynamic power varies across combinations of core voltage and percentage of high-speed versus low-power logic.
Leveraging FPGA logic architecture and interconnect fabric can deliver a very high efficiency and performance. Utilizing this architectural combination can allow more logic to be packed with less routing, thus increasing performance and reducing power.
Adaptive logic module (ALM) technology in FPGAs maximize performance and minimize power by implementing 80% more logic functions than competitive architectures. Further, FPGAs utilizing interconnect architecture can maximize performance, minimize congestion, and minimize power. Interconnects provide the connectivity between different LABs and can be measured by the number of “hops” required to get from one LAB to another. Adding interconnect hops increases capacitance, the fewer the hops, the less high-speed logic required to meet performance. The combination of ALM and interconnect architectures allows more logic to be packed with less routing, thus increasing performance and reducing power.
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow. Bringing power optimization into the design flow of area-optimized designs can enable power reductions of 10% to 40% over standard performance. Software optimization tools automatically use the FPGA architecture capabilities to further reduce power.
Conclusion
While the move to very small process nodes, 65-nm and below, delivers the expected Moore's Law benefits of increased density and performance, the performance increases will result in significant increases in power consumption. If power-reduction strategies are not employed, static power consumption increases to critical levels. Additionally, without specific power optimization efforts, dynamic power consumption will rise due to increased logic capacity and higher switching frequencies. Overcoming these power challenges with an enabling and innovative architecture combined with process technology and circuit techniques advancements can provide an efficient and scalable solution for today’s increasingly complex FPGA-based designs.
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Figure 1, Figure 2, Figure 3 Figure 4, Table 1
