Handheld battery powered equipment such as PDAs, smartphones and portable navigation systems are typically powered by advanced RISC machine (ARM)-based processors. Several device families are available from different manufacturers such as:

• Texas Instruments OMAP processors


• Intel XScale processors


• Samsung S3C2xxx-Series

In all of these processors, several types of power-save modes are implemented. So called ‘idle’ and ‘sleep’ modes are based usually on the fact that processor power can be reduced by switching off part of the internal circuits of a processor if not used. Typically, this is done internally by turning off the clock signal to these blocks, but also can be done by turning off or reducing the supply voltage in some power-save modes.

The more advanced the processors, the more different supply voltages are needed to power it. This can be done by several single converters such as standard low drop out voltages (LDO) or step-down converters. As the power source is typically a LiIon cell, step-down converters provide higher efficiency for output voltages below 3.3V, which is typically the case in such applications. However, for some of the supply voltages it makes sense to use LDOs. A phased locked loop (PLL), which is used to generate the internal clock signals in a processor, is sensitive to any noise. As such, an LDO is required to supply this part of the processor. As the current for this block is typically in the 5mA to 30mA range, the impact on total efficiency is low. The same is true for the supply for a real time clock (RTC). When the LDO can be powered from a voltage that is close to the output voltage needed, an LDO can be a simple, inexpensive and efficient solution. In applications using an I/O voltage of 1.8V, the PLL-LDO could be powered from that rail, providing it has an output voltage of 1.3V with an efficiency of 72 percent.

 

Because several different voltages are needed, there is a demand for integrating the converters into one package. This provides different voltages with one single power supply chip eliminating the need for stand alone chips with all the additional circuitry for sequencing, and for generating a proper reset signal to the processor.

Table 1 shows the various processors where the internal clock can be reduced to minimize power consumption. Additionally, the processor core supply voltage is reduced with lower clock frequency. In OMAP1710 and Samsung S3C2440, the core voltage is simply set to a fixed lower voltage. The Intel PXA270 processor is slightly different in this respect. The core voltage can be set to two different voltages, while also able to be scaled to any voltage between a minimum and maximum – depending on internal clock frequency the “work load.” This method is called dynamic voltage scaling (DVS). The converter supplying the core voltage has to be capable of reducing its output voltage during operation based on the specifications for DVS.

There are two parameters to be considered: 1) output voltage range; and 2) slope during voltage change. During a DVS cycle when the voltage is changed, the slope of the output voltage must be controlled. This can be done with external components such as a capacitor that slows down the change of reference voltage internally. Or this can be done by implementing a digital counter that changes the output voltage from the initial value to the new target in small steps, such as with a 25mV step-size. An internal register in the power supply is used to set the timing between the different steps. Thus, the power supplies for mobile processors usually contain a digital interface to control their functions.

Block diagram of the TPS65020

In order to provide power to the different supply rails for a processor, the TPS65020 integrates three highly efficient, synchronous step-down converters and two LDOs. Additionally, in place is all the circuitry necessary to supervise the battery voltage and to provide reset and wakeup signals to the processor (Figure 1).

Setting the output voltage

 

With decreasing voltage levels the requirement on output voltage accuracy, especially for the core supply, is very tight. This makes it challenging for power supply designers to meet these requirements with standard devices, which is why the TPS65020 was designed with this new approach in mind. The output voltage of the converters implemented in the TPS65020 can be set in a unique way. (See Figure 2.) The DEFDCDCx pins, which are used to set the output voltage, can be used as a digital input as well as an analog input for the feedback voltage divider. If an external feedback voltage divider is used, the tolerance of the resistors add to the total tolerance of the internal circuitry – mainly, the bandgap voltage tolerance. The total accuracy in such a system is always less than desirable when compared to solutions using an internally fixed output voltage despite the fact that there are two additional external components needed. Typically, the voltages for the different converters are known in the application. There is a 3.3V rail for the I/O, a 1.8V rail for the memory, 1.3V for the core, etc.

Therefore, it makes sense to define a set of different voltages for the converters using an internal resistor divider which can be trimmed during production. With such an approach, a total DC accuracy of +/-1 percent over a temperature range from -40ºC to 85ºC can be achieved. Using an internal, high-precision resistor divider, the DEFDCDCx pins are used also to set the voltage of the converter to one of two different pre-defined output voltages. For instance, the voltage for the DCDC1 converter can be set to 3.3V by connecting DEFDCDC1 to Vbat or to 3.0V by connecting it to GND.

For a small tolerance of the output voltage also under different load conditions, and especially for best transient response, there are other measures that must to be taken. In addition to the internal design, the external components need to be optimized. When the output current of an inductive step-down converter is increased, the current must be supplied from the output capacitor at the beginning. This is so because the current in an inductor can be increased only with a certain slope, depending on the voltage across the inductor and the inductor value. For a small inductor value, the current can ramp faster. This is why a small inductor value is preferred for fast transient response. Additionally, in each switching cycle energy is stored in the inductor, which is proportional to the inductor value and the square of the current in the inductor. Even if it is not required, this energy must be delivered to the output in case the load current is removed. In this case, the energy is transferred into the output capacitor, charging it to a higher value. Also during a transient condition when the load is removed, a smaller inductor value is an advantage as it will charge only the output capacitor by a smaller voltage and show a small voltage overshoot. Figure 3 shows how the transient output voltage can be influenced by using smaller inductors and different output capacitors.

In order to use such small inductors as 2.2uH, the converter must be designed to operate at a high switching frequency. This is necessary to keep the inductor current ripple in an acceptable range. TPS65020 was designed to operate with a switching frequency of 1.5MHz, allowing the use of small 2.2uH inductors and 22uF ceramic output capacitors. In order to decrease transient voltages, the output capacitor can be increased to higher values.

As shown in Table 1, different processors may require different voltages to power their internal circuitry. TPS65020 was designed to power the Intel PXA270. Therefore, the internal LDOs are set to an output voltage of 1.1V for the SRAM and to 1.3V for the PLL. Figure 2 shows how the power supply is typically set up to provide power to an Intel PXA 270 processor.

Some applications only reduce the internal clock frequency of a processor without changing the supply voltage. In such designs, there is no need for a digital interface like a I2C interface to the power supply chip. In this case, the whole design including the software can be made simpler.

In TPS65020, the LDO voltage is preset to 1.1V for the SRAM and to 1.3V for the PLL inside Intel PXA270. The voltage can be changed using the I2C interface, but in designs without an interface there is no way to set a different voltage.

For such applications, the TPS65021 can be used to provide a means to set the output voltage as well as for the internal LDOs without using the I2C interface. Two external pins can be used to set the default value in a digital way – see Figure 4.

The pins DEFLDO1 and DEFLDO2 are used to set four different voltage combinations for the internal LDOs, making it flexible for a wide variety of portable applications.

In addition to all the measures used in the processor to save power in a portable application, there also are measures for the power supply. Using the latest process technology for the processor and power supply, especially for the inductive step-down converters, helps to increase efficiency by reducing switching losses. For low output current, switching losses can be reduced further by reducing the switching frequency usually referred to as pulse frequency mode (PFM). Synchronous rectification keeps efficiency high at low output voltages as there is less voltage drop on the internal N-Channel MOS (NMOS) when compared to an external rectifier diode, making the application more efficient and smaller due to the integration of the rectifier switch. Low switching losses at low output current will give a highly efficient power supply, as long as the supply current needed in the power supply chip is low. Internal voltage reference, comparators, drivers and amplifiers need to be designed for lowest supply current. With all these measures an efficiency above 95 percent can be achieved over a wide output current range as shown in Figure 5.

In addition to high efficiency, transient response is a key factor in power supply chips for processors (Figure 6). The core voltage especially needs to be regulated very tightly, including the voltage changes during a load change. TPS65020 with its fast voltage mode control topology provides state-of-the-art transient response without compromising quiescent supply current and, therefore, efficiency. These features make TPS65020 an ideal solution to provide processor power for mobile equipment.

Click here for Illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Table 1