Class D amplifiers are essentially switching amplifiers that have more in common with a switched mode power supply (‘SMPS’), an analogy that which will be explored later in this article, than with their linear predecessors. The latter topology exploits the linear characteristic of a transistor, and as the transistors are always on, a linear amplifier can only achieve efficiencies of around 50%. Class D, nevertheless, utilizes a switching topology whereby the MOSFETs are either ON or OFF enabling efficiencies of up to 95% to be achieved.
Market Growth
It is these ‘green credentials’ that enable smaller, more powerful and efficient Class D designs that has seen the technology proliferate into mainstream consumer electronic applications that range from a few watts for LCD TV systems to hundreds of watts for home theatre systems (and into 5kW range for sound reinforcement applications). Gartner, a market forecast group, predicts revenue growth of Class D amplifiers to exhibit a compound annual growth rate, ‘CAGR’ of 15% as revenue for Class D grows to 688M$ by 2011.Furthermore, Gartner highlights particularly explosive growth (34% ‘CAGR’ )for home cinema stereo receivers that outstrips all other Class D segments. As can be seen from Figure 1 an integrated or discrete solution can be adopted for all but the high power solutions where the power requirements dictate a discrete power output stage is implemented. Other factors that will influence the choice of solution are cost and space.
Class D – How it works
Class D amplifier can utilize either half-bridge (two devices) or full-bridge (4 devices). Each topology has its own advantages; for example, half-bridge topologies are simpler (reduced gate drive circuitry), and cheaper (fewer components) to design but may suffer from ‘bus pumping’ phenomena (current transferred back into the supply) if not correctly designed. For reasons of clarity and simplicity only half-bridge topologies will be discussed in this article although it should be noted that the points raised are also relevant to the full bridge topology. A simplified block diagram of a half bridge PWM-based Class D amplifier is shown in Figure 2. It consists of a pulse-width modulator, output stage, and a reconstruction filter to recover the amplified audio signal. The audio input signal (‘1’ on Figure 3 ), of between 20Hz and 20kHz , is compared against a triangular carrier waveform (‘2’ on figure 3) of >25kHz. The output from the comparator is a fixed frequency signal, the pulse width of which varies and is proportional to the input signal (‘3’ on figure 3). This PWM signal is fed into the gate drive circuitry whose function is to provide a relatively high current pulse to charge/discharge the MOSFET gate capacitance to turn ON/OFF the MOSFETs. The resultant amplified signal is then fed via a reconstruction filter that strips out the carrier frequency from the pulse width modulated signal, to leave the amplified audio signal which drives the loudspeaker.
As eluded to earlier in the article, Class D and ‘SMPS’ share essentially the same topology. The main differences are firstly, that the input signal to a SMPS is a slow changing reference signal (from a feedback circuit) whereas the input to a Class D amplifier is a continuously changing audio signal. Secondly, the characteristics of MOSFETs are optimized differently. In an SMPS, the high side MOSFET is optimized for gate charge (Qgd) and the low side for on-state resistance RDS(on) in order to maximize efficiency. However, in Class D designs the same MOSFET specification is utilized in both the low and high side positions.
The ideal amplifier
Due to the switching characteristics of the topology, Class D amplifiers are often wrongly referred to as ‘digital amplifiers’. However, this can be misleading as Class D designs can utilize an analogue modulator, such as the ZXCD1210 or a digital modulator like the ZXCZM800. The main benefit of processing the audio signal in the digital domain is the maintenance of signal resolution and goes some way towards achieving the ideal Class D amplifier; one that amplifies audio frequency signal with zero distortion, generates no noise, has zero output impedance and delivers a 100% efficiency. However, in real world Class D amplifiers imperfections of noise and distortion are generated by the switching circuit in the gate drive and power stage. The main problems are:
1. Switching Dead-time, required to avoid unacceptable shoot through currents
2. Variations in FET switching performance, and Rds-on modulation.
3. Power supply ripple and noise, injected directly to the output in the absence of an effective feedback mechanism
Optimizing MOSFETS for Class D
The selection of the optimal MOSFET for use within the power stage will address some of the issues identified in points 1 and 2 previously and will influence the performance of the output stage. Once the appropriate device breakdown voltage (BVdss) has been selected for the Class D MOSFET, the key characteristics, in order of importance are its: reverse recovery (Qrr/trr); since this influences EMI; its gate charge (Qgd) as this influences switching losses; and, its RDS(on) because this influences on-state losses.
Electromagnetic interference is more problematic in Class D applications than in other switching applications due to its impact on the audio signal. One of the major sources of EMI and distortion is the reverse recovery (Qrr) of the body diode that is inherent to the MOSFETs structure. ‘Dead Time’ is a period of non-conduction that is enforced to prevent both the high and low side MOSFETs being turned on at the same time and is generally accepted as a source of distortion. During this ‘dead time’ period current from the inductive element of the low pass filter turns on the body diode. The resultant waveform (Figure 4a) is a source of EMI and distortion and can be minimized by selecting a MOSFET with a low Qrr parameter. Figure 4b compares the Qrr response for a Zetex MOSFET against competitor devices. As can be seen the Zetex device has the lowest Qrr and would therefore be best suited to Class D applications.
After Qrr, gate charge (Qgd) is the next important parameter for a Class D MOSFET. Gate charge is the capacitance that has to be overcome when the device switches on, the lower the Qgd the faster the device turns on which minimizes the switching losses. Switching losses in the MOSFET can also be attributed to the rise/fall time and propagation delay in the gate drive circuitry. For example, the difference between 20 and 40nS propagation delays can equate to 100 fold increase in harmonic distortion due to the non-linearity introduced at the switching stage.
Finally, the on-state losses (RDS(on) ) of the device will determine the conduction losses; the lower the RDS(on), the lower the conduction losses.
Due to practical manufacturing tolerances there will be differences between the Qrr, Qgd and RDS(on) of the low side and high side MOSFETSs. These differences can contribute to mismatches between channels and can be sources of noises. By specifying MOSFETs, such as the ZXM10A09K, and gate drivers with narrow minimum and maximum limits for these key parameters, semiconductor manufacturers such as Zetex are aiding designers in achieving optimized power stages of Class D amplifiers
The benefits of feedback
Introducing feedback from the output stage back into the PWM signal will improve the linearity of the amplifier and provide the amplifier with power supply rejection. By comparison, an open-loop amplifier has an inherently minimal supply rejection. Because the output waveform is sensed and fed back to the input of the amplifier in a closed-loop topology, deviations in the supply rail are detected at the output and corrected by the control loop. The advantages of a closed-loop design come at the price of possible stability issues, as is the case with all systems that make use of feedback. Therefore, the control loop must be carefully designed and compensated to ensure stability under all operating conditions. One such approach, developed by Zetex, is the Direct Digital Feedback Amplifier (DDFA). This comprises a feedback processor (ZXCZA200) and a multi-channel digital modulator (ZXCZM800). The basic principle of operation is to establish the pulse area error and feed this back to the digital domain where compensation can be made. Figure 5 shows the feedback topology of a DDFA.
Conclusion
Highly efficient, Class D amplifiers now achieve a comparable performance to that of their linear predecessors. By processing the audio signal in the digital domain, a high level of audio signal resolution is attained and goes some way to achieving the ideal amplifier, although the switching power stage of the amplifier remains a design challenge. Sources of distortion and interference can be minimised in Class D output stages by selecting MOSFETs and gate drivers optimised for Class D applications and introducing a feedback topology to improve power supply rejection.
Click here for Illustrations:
Figure 1, Figure 2, Figure 3, Figure 4a, Figure 4b, Figure 5
